Abstract: Manufacturing a semiconductor device with higher operating characteristics and achieve low power consumption of a semiconductor integrated circuit. A single crystal semiconductor layer is formed so that crystal plane directions of single crystal semiconductor layers which are used for channel regions of an n-channel TFT and a p-channel TFT and which are formed over the same plane of the substrate are the most appropriate crystal plane directions for each TFT. In accordance with such a structure, mobility of carrier flowing through a channel is increased and the semiconductor device with higher operating characteristics can be provided. Low voltage driving can be performed, and low power consumption can be achieved.

Abstract: There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed.

Abstract: A thin-film transistor uses a semiconducting layer comprising a semiconducting material of (A): where X, Ar, Ar?, R1, R2, R3, R4, R5, a, b, m, and n are as defined herein. The transistor has improved performance.

Abstract: A semiconductor light-emitting device member excellent in transparency, light resistance, and heat resistance and capable of sealing a semiconductor light-emitting device without causing cracks and peeling even after a long-time use is provided wherein the semiconductor light-emitting device member contains (A) in a solid Si-nuclear magnetic resonance spectrum, at least one peak selected from (a) peaks whose peak top position is in an area of a chemical shift of ?40 ppm to 0 ppm inclusive, and whose full width at half maximum is 0.3 ppm to 3.0 ppm inclusive, and (b) peaks whose peak top position is in an area of the chemical shift of ?80 ppm or more and less than ?40 ppm, and whose full width at half maximum is 0.3 ppm to 5.0 ppm inclusive, wherein (B) silicon content is 20 weight % or more and (C) silanol content is 0.1 weight % to 10 weight % inclusive.

Abstract: A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.

Abstract: An example photodetector includes a waveguide structure having an active waveguide comprising an absorber for converting photons conveying an optical signal into charge carriers conveying a corresponding electrical signal; a carrier collection layer for transporting the charge carriers conveying the electrical signal; and a secondary waveguide immediately adjacent to the carrier collection layer, for receiving the photons to be detected, and which is evanescently coupled to the active waveguide.

Abstract: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.

Abstract: A semiconductor device that has a pMOS double-gate structure, has a substrate, the crystal orientation of the top surface of which is (100), a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first <110> crystal orientation, and channels are located at sidewall of the semiconductor layer, a source layer that is formed on the substrate adjacent to one end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a drain layer that is formed on the substrate adjacent to the other end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a gate electrode that is formed on the semiconductor layer in a direction of a second <110> crystal orientation perpendicular to the curre

Abstract: A semiconductor package includes a semiconductor device having a first main surface and a second main surface, a first electrode plate provided on the first main surface, a second electrode plate provided on the second main surface, and a wiring substrate provided between the semiconductor device and the first electrode plate, in which a plurality of opening portions in the side surface of a protruding portion provided on the first electrode plate are engaged respectively with a plurality of engaging portions which face the opening portions and which are provided on the inner side surface of an intrusion opening portion in the wiring substrate into which the protruding portion is intruded.

Abstract: A Schottky diode includes at least a trenched opened in a semiconductor substrate doped with a dopant of a first conductivity type wherein the trench is filled with a Schottky junction barrier metal. The Schottky diode further includes one or more dopant region of a second conductivity type surrounding sidewalls of the trench distributed along the depth of the trench for shielding a reverse leakage current through the sidewalls of the trench. The Schottky diode further includes a bottom-doped region of the second conductivity type surrounding a bottom surface of the trench and a top-doped region of the second conductivity type surrounding a top portion of the sidewalls of the trench. In a preferred embodiment, the first conductivity type is a N-type conductivity type and the middle-depth dopant region comprising a P-dopant region.

Abstract: An image sensor is provided. The image sensor can include a semiconductor substrate including a circuit region, an interlayer dielectric including a metal interconnection on the semiconductor substrate, a lower electrode on the metal interconnection, and a light receiving portion on the lower electrode. The light receiving portion can be a PIN diode formed to have a convex shape.

Abstract: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.

Abstract: A semiconductor device includes: a circuit board; a semiconductor chip mounted over the circuit board with a predetermined gap therebetween and electrically connected to the circuit board by a protruding electrode; a first resin material filled into the gap between the circuit board and the semiconductor chip; a second resin material that seals the semiconductor chip mounted over the circuit board; a first reflector which is formed on a surface of the circuit board on the semiconductor chip side and reflects a predetermined testing light; and a second reflector which is formed on a surface of the semiconductor chip on the circuit board side and reflects the predetermined testing light.

Abstract: A field-effect transistor power device includes a source electrode, a drain electrode, a wide gap semiconductor including a channel region and a drift region, the channel region and the drift region forming a series current path between the source electrode and the drain electrode, a gate insulating film that covers the channel region, and a gate electrode formed on the gate insulating film. In the series current path which is electrically conducting when the field-effect transistor power device is in an ON state, any region other than the channel region has an ON resistance exhibiting a positive temperature dependence, and the channel region has an ON resistance exhibiting a negative temperature dependence. A ratio ?Ron/Ron(?30° C.) is 50% or less.

Abstract: Aspects of the present invention provide an enhancement mode (E-mode) insulated gate (IG) double heterostructure field-effect transistor (DHFET) having low power consumption at zero gate bias, low gate currents, and/or high reliability. An E-mode HFET in accordance with an embodiment of the invention includes: top and bottom barrier layers; and a channel layer sandwiched between the bottom and the top barrier layers, wherein the bottom and top barrier layers have a larger bandgap than the channel layer, and wherein polarization charges of the bottom barrier layer deplete the channel layer and polarization charges of the top barrier layer induce carriers in the channel layer; and wherein a total polarization charge in the bottom barrier layer is larger than a total polarization charge in the top barrier layer such that the channel layer is substantially depleted at zero gate bias.

Abstract: The present invention discloses a surface mount type light-emitting diode package device and a light-emitting element package device. In the device, the encapsulation layer comprises an encapsulation material and at least one material having a refraction index different from the encapsulation material distributed therein. The distribution of the material having a refraction index different from the encapsulation material is in a way such that the refraction index of the encapsulation layer is gradually reduced from the bottom portion upward to the top portion or the inner portion outward to the outer portion of the encapsulation layer. Accordingly, a difference between the refraction indexes of two adjoining media can be reduced to eliminate a total reflection and the Fresnel loss and enhance light extraction efficiency.

Abstract: An electronic apparatus comprising one or more microstructures on a substrate and a method for fabricating the electronic apparatus. The microstructures have alignment structures that allow the microstructures to be oriented in receptacles having shapes that are complementary to the shapes of the alignment structures. The alignment structures are shapes that vary when rotated 360°, such that the microstructures are positioned at a specific orientation in the receptacles.

Abstract: Separate first and second floating gates for attracting carriers transferring in a transistor structure having a channel region and first and second main electrode regions into charge storage films therebelow are formed so as to largely face a control gate. The control gate between the separate first and second floating gates faces to the channel region via thin interlayer insulating layer. Therefore, a semiconductor device according to the present invention can inject electrons the charge storage film without causing writing errors in a writing operation, and therefore can increase in reliability thereof, control a writing voltage, prevent loss of the electrons stored in the charge storage film, and reliably apply a bias voltage to a channel region.

Abstract: A resistive circuit includes a first terminal and a second terminal and polycrystalline first and second resistive segments coupled between the first and second terminals. A third terminal A is coupled to the first resistive segment, and a third terminal B is coupled to the second resistive segment. The third terminal A has a first voltage with respect to the first terminal, and the third terminal B has a second voltage with respect to the second terminal. With this arrangement, the non-linearity of resistance of the first resistive segment at least partially compensates for non-linearity of resistance of the second resistive segment.

Abstract: A method for forming a fine pattern of a semiconductor device includes forming a deposition film over a substrate having an underlying layer. The deposition film includes first, second, and third mask films. The method also includes forming a photoresist pattern over the third mask film, patterning the third mask film to form a deposition pattern, and forming an amorphous carbon pattern at sidewalls of the deposition pattern. The method further includes filling a spin-on-carbon layer over the deposition pattern and the amorphous carbon pattern, polishing the spin-on-carbon layer, the amorphous carbon pattern, and the photoresist pattern to expose the third mask pattern, and performing an etching process to expose the first mask film with the amorphous carbon pattern as an etching mask. The etching process removes the third mask pattern and the exposed second mask pattern.