Abstract: An inter-network connection system wherein a local signaling network including gateway offices of at least two signaling networks to be interconnected is configured between the signaling networks to be interconnected, and the inter-network connection is carried out through the local signaling network.

Abstract: It has been observed that the S/N ratio of differential-mode PCM and summation-mode PCM with respect to quantization noise is improved at low frequencies and high frequencies, respectively, and consequently the dynamic range thereof is increased. An input signal is divided into blocks of a predetermined number of bits, and, for each block, the one of the general-mode PCM, differential-mode PCM, and summation-mode PCM mode is selected in which adaptive encoding is most efficient, and consequently the quantization noise is smallest, and the input signal data in the mode selected for each block is transmitted together with a mode signal and an adaptive data signal, etc. It has also been observed that the closer to the main signal, the larger the masking effect on the sense of hearing, so that the S/N ratio in terms of the sense of hearing is improved by changing the noise spectrum during digitization to correspond to the spectrum of the input signal.

Abstract: A Digital Pulse Processor (DPP) designed to accept pulsed inputs and produce digital pulse descriptor word (PDW) outputs accepts pulsed signals from three adjacent channelized inputs. The DPP then derives a measurement of pulse amplitude from the peak value in the center frequency channel. The relative peak amplitudes between channels are used to establish aa fine frequency offset. The fine frequency offset is used in conjunction with coarse frequency inputs to compute a pulse frequency estimate. An internal counter generates a time reference for time of arrival (TOA) and pulse width measurements. The TOA and pulse width measurements are based on calculations to establish three dB points on the leading and trailing edges of the pulse. This pulse characterization information is produced in real time at the optimum signal-to-noise ratio, and is independent of incoming amplitude, rise/fall time, and pulse width.

Abstract: A fault tolerant circuit and method of synchronizing multiple asynchronous input signals, such as reset signals, in a modular redundant fault-tolerant computer system in which clock signals or respective slices have a bounded skew with respect to one another. The input signal and clock signal for each slice of the system are used to produce an initial synchronization signal in each slice of a first layer of the circuit. Each initial synchronization signal is used with an inverted version of each of the slice clock signals to produce, in each slice of a second layer of the circuit, a set of local synchronization signals for each slice. The local synchronization signals for each slice are passed to a majority-voter which produces a voted output signal for the slice. The voted output signal and the clock signal for each slice are then used to produce a finally synchronized output signal for that slice.

Abstract: A method and apparatus for equalizing pulse widths of a digital signal. In digital communications transmission systems, the transmitted digital signals are regenerated using line equalizers. Since higher requirements exist for the equalization with digital clock recovery equipment, it is necessary to again equalize the pulse widths. The beginning of the pulses of the equalized digital signal (D3) is obtained from the leading edges of the pulses of the digital signal (D2) which is to be equalized and the end of the pulses of the equalized digital signal (D3) is obtained from the leading edges of the pulses of an auxiliary data clock (DHT). The equipment can be an integrated circuit which has two D-flipflops (22, 23) that alternately process the pulses under the control of a JK-flipflop (26). Digital signals (D2) having a bit rate equal to or greater than 34Mbit/s can also be processed.

Abstract: A dual mode LMS channel equalizer is disclosed. The inventive channel equalizer utilizes an LMS algorithm to both identify channel parameters and to smooth the received data signal to mitigate the effects of channel additive noise. In real time operation, the inventive equalizer first identifies the channel parameters in a training period. Thereafter, the same LMS algorithm is switched to smooth the received data signal, while intermittently, the LMS algorithm is switched back to track the slowly changing channel parameters. In comparison with the conventional LMS adaptive channel equalizer, the inventive dual mode channel equalizer achieves a significant performance improvement at little additional cost.

Abstract: An adaptive predistortion circuit for a digital transmission system includes a predistortion circuit (52.sub.1, 52.sub.2, 52.sub.3) for predistorting the input data before they pass through a modulator (56) and then through an amplifier (57), and an adaptation circuit (61.sub.1, 61.sub.2, 61.sub.3) for continuously adapting the predistortion circuit to the stream of input data in response to a demodulation of the stream of transmitted data. The predistortion circuit further includes an encoder (51) which, on a first path, in response to digital data a.sub.k, generates digital data b.sub.k which leave a first predistortion circuit (52.sub.1) in a predistorted manner in-phase with the symbol clock, on a second path, digital data c.sub.k which leave a second distortion circuit (52.sub.2) in a predistorted manner phase-shifted by T/3 relative to the symbol clock and on a third path, digital data d.sub.k which leave a third predistortion circuit (52.sub.

Abstract: A polarity detector for subscriber lines in a data transmitting system which detects the polarity of 2-wire subscriber lines using 2B1Q codes. A converter converts a quaternary 2B1Q code into binary code and outputs complementary binary data. A frame synchronizing signal detector detects a binary code frame synchronizing signal in the complementary binary data and outputs a timing signal. A pattern detector detects an all "1"s or "0"s state of the complementary binary data and the timing signal. A selector circuit selects all complementary data having a single polarity in response to all "1"s or "0"s detected by the pattern detector. Therefore, correct data is received by correctly detecting the polarity of the subscriber line.

Abstract: A circuit arrangement has a control logic stage, a clock monitoring stage, and a clock selector stage. The control logic stage includes a shift register having register cells that are identical with the exception of the first. The identical shift registers have a D-flip-flop in which a pre-control signal is formed by intermediate storage of a control signal. A pre-control signal arises in the first register cell when all other pre-control signals are absent. The switching ensues dependent on a correction signal and the clocks at the affected registered cells such that the previous control signal is first disconnected before the new control signal is engaged. In the clock selector stage, the active control signal through-connects the allocated clock as auxiliary data clock. The clock monitoring stage generates a start signal when either no control signal is present or when a plurality of control signals were erroneously formed at the same time.

Abstract: In an antenna-selection diversity transmission and reception equipment which is in digital communication with a transmission and reception equipment having a single antenna, and performs transmission and reception with time division by using the same radio frequencies, the antenna-selection diversity transmission and reception equipment comprises a plurality of antennae, a receiving part having a receiving unit, comparing unit and selecting unit which are adapted for a receiving-antenna selection diversity, and a transmitting part having a memory unit for storing antenna information that was selected by the receiving part. An antenna for transmission is selected from the plurality of antennae at the time of transmission in accordance with the information of the memory unit.

Abstract: A circuit for filtering pulse sequences of a given frequency out of a composite signal includes a series combination of a monostable multivibrator (MF) and a random-access memory (RAM), an address register and a clock. The monostable multivibrator (MF) serves as a pulse shaper of incoming signals. The input (D.sub.E) and output (D.sub.A) of the random-access memory (RAM) are connected to the inputs of an AND gate (UG). An address counter register (AR) associated with the random-access memory (RAM) has a count cycle whose duration is equal to the pulse spacing of the sequence to be recognized. During each clock period (T2), the current signal state of the input (D.sub.E) of the random-access memory (RAM) and the content of the addressed memory cell are checked for equality by the AND gate (UG) and the current signal state is then written into the cell.

Abstract: In a digital data recovery receiver, an optimal (in the Maximum likelihood sense) estimate of Es/No (dB) is obtained by the following mechanism. First, over a prescribed symbol span of N symbols, for each of 2.sup.B-1 -1 quantization bins, respectively associated with 2.sup.B-1 threshold levels used by a B-bit resolution analog-to-digital converter to digitize a received signal, the number of times that the received signal is quantized with respect to that level is counted. Each count total is divided by the number N of symbols in the span, to obtain plural ratios, respectively representative of probalities of symbol pseudo error rate over the symbol span. Using these ratios, respective Es/No (dB) values are derived from stored pseudo error relationships, each of which is associated with a respective one of the 2.sup.B-1 -1 quantization bins and defines the probability of symbol error rate in terms of Es/No (dB).

Abstract: A GMSK modem is provided and comprises a baseband modulator section and demodulator section coupled to an FM transmitter and receiver, respectively. The Modulator section includes a digital waveform generator for generating a GMSK baseband signal from a binary digital data source. The output of the waveform generator approximates the baseband signal output of a premodulation filter with a Gaussian impulse response having a normalized noise bandwidth of between 0.25 and 0.45 in series with a gain controlled amplifer. The gain is adjusted such that the modulation index of an RF signal modulated with the baseband signal is between 0.5 and 0.7.The demodulator section receives the analog output of a discriminator-based FM receiver with a phase equalized Butterworth IF filter. The demodulator section comprises a binary quantized loop bit timing recovery subsystem and one or the other of two data detectors.

Abstract: Monolithic broadband semiconductor single-pole, double-throw switches are merged into distributed monolithic amplifiers and decrease the total semiconductor chip area occupied by the devices.

Abstract: A broad-band mixing circuit comprises a transmission line transformer connected between a port adapted to receive a radio frequency signal and a double balanced mixing section, the transformer serving to convert an unbalanced radio frequency signal into a balanced signal, a transmission line transformer connected between a local oscillation signal port and the mixing section, the transformer serving to convert an unbalanced local oscillation signal into a balanced signal, and a transmission line transformer connected between the mixing section and an intermediate frequency signal port, the transformer serving to convert the balanced signal from the mixing section into an unbalanced signal. The noise figure is improved by connecting an electrolytic capacitor in parallel with the balanced output end or the input end of the transmission line transformer for the local oscillation signal.

Abstract: A method for correcting quantized waveform data which are formed by quantizing a baseband waveform, so optimized as to make a sum of errors included in a single bit internal of input digital data smaller than one quantization step, and are output as the baseband waveform which is to be accumulated or integrated in the requirement of the system (such as frequency-to-phase conversion). Since an accumulated sum of the quantized waveform data has some deriation from the real baseband waveform when those quantized waveform data are accumulated so as to generate phase information from frequency information, the quantized waveform data have to be corrected previously. For the purpose of reducing the accumulated error, this method involves the steps of defining states corresponding to input data patterns, establishing simultaneous equations corresponding to state transition routes respectively, solving the equations, and deciding correcting values for the quantized data.

Abstract: The adaptive loop gain phase filter of the invention utilizes an averaged value of the phase error at each baud time instead of the phase error for generating the value of the frequency shift. Such an averaged value is obtained by accumulating in accumulator ACCU2 (34) the phase error at each baud time after multiplying it by a factor K.sub.O, and is provided either very M baud time when a counter (38) preset at M reaches O, or if the contents of accumulator (34) reach a predetermined limit value. The value of the frequency shift which is accumulated in accumulator ACCU1 (14) is every accurate and enables the phase disturbance such as line breaks and phase hits to be overcome.

Abstract: An equalizer characteristic of an amplitude equalizer for use in a modulating and demodulating device (MODEM) can be set with considerable ease. One of a plurality of equalization characteristics assigned to an amplitude equalizer is set by generating and feeding to a transmission line a plurality of reference signals at the same level but with respectively-different frequencies. Each of such respective reference signals are received from the transmission line, separated, and measured as to its reception level. Level errors are then determined between each measured reception level and an estimated reception level previously determined in association with a respective one of the equalization characteristics. A selection and setting is then made of one of the equalization characteristics that is associated with one of the estimated receptions levels having the smallest level error.

Abstract: To prevent theft of a car radio (R), the radio unit itself is located in the vehicle (V) in a suitable secure location. The radio is controlled by a two-part control unit, in which one part of the control unit forms a connection part (1), secured to the vehicle, for example, by a goose-neck (5) or the like, and the other part forming a control part (21) which is separable from the connection part. Interengaging dovetail track-and-groove connections permit ready removal of the control part (21) from the connection part, so that a user may remove the control part, and thus not leave any indication in the vehicle that it contains a car radio. The control part contains the necessary control buttons and display functions to operate and control the car radio, the connection part merely including a plurality of contact terminals which, with the control part removed, are depressed below a top surface of a housing (2, 3) of the connection part.

Abstract: A receiver in a spread-spectrum communication system is adapted to receive a signal which is modulated by a binary code modulated by a binary code or a data, and includes a matched filter which detects a correlation between the received signal and a reference signal modulated by a reference code produced by a code generator. When the received code supplied from the matched filter coincides with or is slightly displaced from the reference code, a pulse is produced from a correlation spike waveform with a relatively large amplitude to extract a desired pulse from the pulse and use it to initialize the reference code generator.