Abstract: A millimeter wave device having a dielectric substrate with a pair of substantially parallel planar surfaces with at least one predetermined millimeter wave circuit pattern formed in a conductive layer located on at least one of the substrate surfaces. A substantially planar conductive channel plate is mounted adjacent the conductive layer on one substrate surface with the channel plate having an aperture overlying each circuit pattern formed in the conductive layer. A substantially planar conductive cover plate is mounted adjacent one of the channel plates so as to form a first cavity in the region defined by the substrate surface, the channel plate aperture and the cover plate. The device may further include a second substantially planar conductive channel plate mounted adjacent the other one of the substrate surfaces with the second channel plate having an aperture corresponding to and aligned with the first channel plate aperture.

Abstract: A trunked communication system (100) wherein an EOT (308) as transmitted by a communication unit (103) is used by the system to initiate a squelch methodology, but is not used by the resource controller (101) to determine reallocation of the communication resources.

Abstract: A TVRO receiver for the reception of frequency modulated satellite broadcast signals is provided with the capability of efficiently rejecting image frequencies generated as the received signals undergo intermediate frequency translation. A TVRO tuner, which includes a super-heterodyne circuit having a voltage-controlled oscillator (VCO), means for supplying a controlling tuning voltage to the VCO, and a mixer for combining incoming 1st IF signals with the output frequency of the VCO to reduce the frequency of the 1st IF signals to a selected 2nd IF frequency, is provided with a tracking filter which is adapted to pass only the incoming 1st IF signals and effectively reject any image frequencies generated at the received signal frequencies.

Abstract: A radio warning receiver has a battery or accumulator (7) and means (8) for switching over to battery operation mode when network power (6) fails. Battery power is conserved by turning off (9) power to the end stage (3), placing the warning receiver in a so-called Stand-By Mode, until a control signal is detected (5) which indicates that a warning is to be broadcast. Then, power to the end stage is restored (11) for the duration of the warning broadcast.

Abstract: A frame synchronization circuit is illustrated, which uses an algorithm of reverting to an initial state of selecting the next logic zero data bit in a data bit stream for the potential bit position to be used as a framing bit, and returning to reinitialization if any of the next M-bits in that bit position do not follow a prescribed framing pattern. Once synchronization is established, the detection of three out of five framing bits being in error will cause the circuit to return to an intermediate state in the framing process, whereby any further errors in the next X number of bits will cause reinitialization, but the lack of any further errors in the next X-bits will allow the circuit to confirm that its original bit position choice as framing bit was correct. This allows the circuit to continue operation with the assurance that it is correctly synchronized with the data, and without interrupting data flow for the comparatively long time it takes to synchronize from "scratch".

Abstract: A decoder for Manchester encoded data includes an up/down counter which constitutes a state machine. Consecutive bits with the same binary value in the encoded data bit stream enable the counter, whic is incremented or decremented in dependence upon the relative phase of an output clock signal. Incrementing occurs in response to phase errors of the output clock signal, and decrementing to a count of zero occurs in response to phase assertions indicating a correct phase of the clock signal. The phase of the clock signal is reversed, and the counter reset, if a maximum count is reached in response to repeated phase errors. Such a phase reversal or phase slip is avoided in the presence of single bit errors in the bit stream. The decoded data is derived from the bit stream by sampling in dependence upon the clock signal.

Abstract: A trellis coder has a convolutional encoder which has n states and can progress from a current state to a follower state depending on an input. The state progressions are selected such that they can be represented by a diagram having 90.degree. rotational symmetry. A state transition produces via mapping means by quadrature modulation one of four output carrier signal phases, such that any three state sequence gives rise to a pair of signals having the same phase difference as the pair generated by a corresponding sequence having a position in the diagram rotated by 90.degree. from that of the sequence in question. Input means enable a single bit data input to control the coder state progression so that a given differential output phase always corresponds to the same input bit value.

Abstract: A high-speed modem that transmits and receives digital data on an ensemble of carrier frequencies spanning the usable band of a dial-up telephone line. The modem includes a system for variably allocating data and power among the carriers to compensate for equivalent noise and to maximize the data rate. Additionally, systems for eliminating the need for an equalization network, for adaptively allocating control of a channel, and for tracking variations in line parameters are disclosed.

Abstract: Contained within a single housing (120), is a transducer (100) for receiving an acoustic signal, an analog-to-digital converter (108), which changes the output of transducer (100) into a series of digital pulses representing the incoming acoustic signal. The output of the system may be in serial form. This serial output (114) is transmitted (116) to a remote receiver (122) by wires, light, optical fibers, or as radio waves. The receiver's (122) output (124) is applied to a digital system (130), which processes or reconstructs the acoustic signal. The system may include a digital signal processor (300) within the housing (120) for processing the signal (110) prior to transmission. The analog to digital converter may be a delta-sigma oversampling type, or a sub-ranging floating point type, or use adaptive differential pulse code modulation. Power may be derived remotely by transmission over the signal medium.

Abstract: A signal equalizing arrangement comprises a decision feedback equalizer formed by a feedforward filter section (16) connected to a feedback filter section (18) which includes a decision stage (20). If the performance of the equalizing arrangement as determined by the signal to noise ratio versus the bit error rate is found to be below the calculated optimum performance of the decision feedback equalizer, then an improved performance may be obtained by operating the equalizer in a time reverse mode. In order to operate the equalizer in a time reverse mode, a first last-in, first-out store (60) is connected in the signal path to the feedforward filter section (16) and a second last-in, first-out store (62) is connected to the output of the decision stage (20).

Abstract: The invention provides a digital clock circuit for providing an output clock signal having a frequency varying between predetermined limits. A digital frequency changer circuit is responsive to a fixed frequency signal and to control signals for generating the output clock signal. A circuit means is responsive to a variable reference signal and to the output signal of the clock circuit for generating a binary control word representative of a frequency difference therebetween. A rate multiplier circuit is responsive to the binary control word and the output clock signal for generating the control signals. The only non-digital component of the clock circuit is a local crystal oscillator.

Abstract: A transceiver for a LAN is capable of communicating multiple bits per signal element to increase the data throughput of the LAN. The transceiver includes a transmitter which receives a multiple bit digital input value originating at a node of the LAN at which the transceiver is present. The transmitter converts the multiple bit digital input signal into a pulse-like analog signal which is amplitude and phase modulated. A receiver of a transceiver at a receiving node the transmitted analog signal converts its amplitude and phase into a corresponding multiple bit digital output value. A time-domain filter of the receiver creates a primary signal from the received analog signal. To sample the primary signal at its maximum amplitude point, a derivative of the primary signal waveform is used to establish the zero derivative point at which the primary signal attains its maximum amplitude, and to establish a fixed sampling point for subsequent signals.

Abstract: Synchronization conditions of a Viterbi decoder are detected using the differences between minimum branch metrics and corresponding minimum path metrics. In accordance with the invention, zero differences are monitored, non-zero differences are monitored and weighted, and the monitoring is used to detect in-synchronization or out-of-synchronization condition of the decoder. More particularly, the differences are non-linearly mapped (F3) into a value in a first set for some differences or a value in a second set for the other differences. In accordance with the method of synchronization detection, an accumulator, counter or indicator is initialized (F1) to an initial value and as the mapped values are produced in sequence, they are sequentially summed (F5) with the value of the accumulator, counter or indicator so as to continually update the sum. The value of the accumulator, counter or indicator is compared to an out-of-synchronization threshold and to an in-synchronization threshold (F6, F7).

Abstract: In a baude rate sampling type receiving circuit for use in a system for transmitting digital data signal at a transmission baude rate, in order to control the sampling phase at the optimum phase, desired elements of an autocorrelation function of a series of baud rate sampled signals are calculated and are linearly summed by a calculating circuit to provide a linear summation as a power of the series of sampled signals. The sampling phase at the baud rate sampling is controlled by a control circuit by use of the linear summation so that the power is maximized, whereby the sampling phase is maintained at the optimum sampling phase.

Abstract: A radio communication apparatus includes a power supply device which includes a solar battery connected to each of a plurality of communication channels via respective switches. A controller constantly monitors the voltage of the solar battery to turn on or off the switches stepwise, so that the number of active channels is reduced stepwise with the decrease in the capacity of the solar battery. The rate of decrease in the capacity of the solar battery is reduced to shorten the period of time during which communication is prevented, whereby operation is insured over a long period of time. Further, communication, (i.e., power consumption) is averaged to reduce the required capacity of the solar battery.

Abstract: In a radio employing continuous tone or digital coded squelch system, fast settling tone processing circuitry is disclosed for a tone processing path which includes an FM detector, low pass filters and a tone limiter. In an exemplary embodiment, a capacitor at the output of the FM detector in the tone/data processing path is charged as rapidly as possible to a new DC level, for example, by an off frequency transmitter. A pulse is generated by, for example, the transceiver microprocessor which initiates the rapid charging of the capacitor as soon as it is detected that data needs to be read from the tone/digital data processing circuitry for decoding. Such a pulse is generated by the microprocessor whenever channel frequencies are changed and/or the carrier activity sensor becomes active.

Abstract: A signal processing apparatus is provided for recovering the clock signal and data signal from an encoded information signal. The encoded signal which is to be processed includes first symbols exhibiting a first frequency representing logical ones and second symbols exhibiting a second frequency representing logical zeros. A tapped delay line produces a first recovered clock signal exhibiting a frequency approximately twice that of the clock rate of the data signal. Circuitry is provided for recovering the data signal and a second recovered clock signal which exhibits a frequency approximately equal to the clock rate of the data signal.

Abstract: An improved circuit for providing automatic gain control (AGC) for incoming phase shift keyed (PSK) and quadrature amplitude modulated (QAM) signals. An absolute value circuit (193) and a comparator (195) provide a first error signal (197). An integrater (200,202) smoothes the first error signal (197) to provide a second error signal (201) to a variable-threshold threshold detector (204). The threshold (209) is initially set at a low value to allow the AGC circuit to quickly respond. A larger value is then used to reduce susceptibility to noise and provide for proper QAM operation. An error circuit (208,211,213) provides a non-linear response so that the gain variations will be small when the input signal (190) is large. This non-linear response further reduces the effects of noise on the AGC circuit.

Abstract: An output clock signal is synchronized with predetermined phase accuracy relative to an internal stable frequency reference clock signal upon the application of a transition of an asynchronous event signal. A plurality of phase shifted versions of the reference clock signal are derived. Upon the occurrence of the asynchronous signal, the states of the phase shifted versions are sampled, and that information is utilized as a code to select one of the phase shifted versions from which the output clock signal is derived. Synchronization occurs rapidly within the metastable settling time of the flip-flops of a register which sample or decode the states of the phase shifted versions, or by logical gating arrangements which avoid the necessity for considering the metastable signal. Synchronization is typically obtainable in less than the period of one reference clock signal.

Abstract: A method for allocating RF communication resources among RF communication systems. This allocation may be base strictly upon demand or it may be based upon the loading of an RF communication system or the relative loading among a group of RF communication systems.