Patents Examined by Ramamohan R. Paladugu
  • Patent number: 5563092
    Abstract: A substrate for use to form an amorphous semiconductor having excellent characteristics, and an amorphous semiconductor substrate comprising a substrate of this kind are disclosed. A method of producing the amorphous semiconductor substrate is also disclosed. An amorphous semiconductor such as a--Si, a--Si alloys, or the like is deposited on a substrate by utilizing an RF plasma having a frequency greater than 50 MHz in an atmosphere whose partial gas pressure associated with a residual gas other than inert gas and hydrogen is less than 10.sup.-8, while applying a bias voltage including a DC component to the substrate during the deposition process. The present invention is characterized in that the substrate has a surface layer having an amorphous structure wherein electric charges may move at least through said surface layer.
    Type: Grant
    Filed: April 22, 1994
    Date of Patent: October 8, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuaki Ohmi
  • Patent number: 5527731
    Abstract: A surface treating method of the invention comprises the steps of generating mixed chemical species containing an intended chemical species of ions necessary for surface treatment by ionization of a gas, selectively trapping the intended chemical species from the mixed chemical species, exciting the intended chemical species to predetermined vibrational and electronic states, extracting the excited chemical species from a position where trapped, and subjecting the extracted chemical species to surface treatment on a surface of an article to be treated. In this method, the intended chemical species of ions which are under vibrational and electronic conditions effective for the surface treatment and have a certain mass number have been once trapped at a given position. The trapped ions are uniformly arranged with respect to their translational velocity and applied to a sample surface. Thus, dry etching with high anisotropy and high selectivity to material and deposition with good uniformity can be realized.
    Type: Grant
    Filed: November 10, 1993
    Date of Patent: June 18, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Yamamoto, Kozo Mochiji
  • Patent number: 5407858
    Abstract: To provide a GaP red light emitting element substrate which a large amount of oxygen is doped in the p-type GaP layer, and which very few Ga.sub.2 O.sub.3 precipitates develop on and/or in p-type GaP layer, and methods of manufacturing said substrate. After the n-type GaP layer 2 is grown on the n-type GaP single crystal substrate 1, when forming the p-type GaP layer 3 doped with Zn and O, on said n-type GaP layer 2 by means of the liquid phase epitaxial growth method, the p-type GaP layer 3 is grown by using a Ga solution with a high concentration of oxygen, and said Ga solution is removed from the substrate 1 to complete the growth when the temperature is lowered to a prescribed temperature of C. or higher. When the temperature has reached the prescribed temperature of C.
    Type: Grant
    Filed: April 12, 1994
    Date of Patent: April 18, 1995
    Assignee: Shin-Etsu Handotai Co. Ltd.
    Inventors: Munehisa Yanagisawa, Yuuki Tamura, Susumu Arisaka, Hidetoshi Matsumoto
  • Patent number: 5403775
    Abstract: The disclosure is directed to improved techniques and devices employing an aluminum-bearing III-V semiconductor material and a native oxide of aluminum that is formed in the semiconductor material. Effective optical confinement, tailored to obtain desired operating conditions, can be achieved with a thick native oxide of aluminum that extends through at least one-third of the thickness of the aluminum-bearing layer in which the native oxide is formed. The resultant lateral index step can be made quite large and employed for devices such as ring lasers.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: April 4, 1995
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Nick Holonyak, Jr., Fred A. Kish, Stephen J. Caracci
  • Patent number: 5392730
    Abstract: A crystal of a compound semiconductor is deposited on a substrate using a metal organic vapor phase epitaxy within a reaction enclosure having a vertical flow of deposition gas supplied through a gas injector within the deposition enclosure. The deposition gas is supplied in a plurality of divided flow paths in which the flow rates are individually controlled. The injector comprises a plurality of gas jet ports which receive respective, plural flow paths and which are disposed in a two-dimensional array having dimensions corresponding to the two-dimensional main surface dimensions of the substrate thereby to supply a uniform flow of deposition gas over the entire two-dimensional main surface of the substrate. The method and apparatus have special application in the deposition of quaternary III--V compound semiconductor.
    Type: Grant
    Filed: September 2, 1993
    Date of Patent: February 28, 1995
    Assignee: Fujitsu Limited
    Inventors: Makoto Kondo, Hiroshi Sekiguchi
  • Patent number: 5380669
    Abstract: Disclosed is a method of fabricating a two-color radiation detector, and two-color photodetectors fabricated by the method. A structure is grown upon a substrate (10) to provide, in sequence, a LPE grown LWIR n-type layer (12), a MWIR p+ type common contact layer (14), and a MWIR n-type layer (16). Following growth of the MWIR n-type layer, a layer of passivation (18) is applied, and the substrate is removed to so as to enable further processing of the structure into an array (1) of two-color photodetectors. The three layer structure is bonded, prior to further processing, to a supporting substrate (22) with an adhesive bond made to the passivation layer. The supporting substrate is comprised of IR transparent material such as Group IIB-VIA semiconductor material, Group IIIA-VA semiconductor material, Group IVA semiconductor material, sapphire, and combinations thereof.
    Type: Grant
    Filed: February 8, 1993
    Date of Patent: January 10, 1995
    Assignee: Santa Barbara Research Center
    Inventor: Paul R. Norton
  • Patent number: 5380677
    Abstract: An interface having low resistance is formed between a single crystal silicon surface and deposited silicon. Before deposition of the silicon, the oxide or nitride layer covering the surface is removed in conventional fashion. The exposed surface is then pre-treated with a plasma etch containing SF.sub.6. Because fluorine is more electro-negative than oxygen, fluorine atoms adhere to the exposed single crystal silicon surface, where their presence prevents reoxidation. Silicon is then deposited on the surface by thermal decomposition of silane, during which deposition the fluorine atoms form silicon-tetrafluoride, which gas is evacuated during a normal out-gas cycle. The resultant interface, which may be an emitter-base junction, exhibits an effective resistance of only a few ohms.
    Type: Grant
    Filed: June 23, 1993
    Date of Patent: January 10, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: John C. Eakin
  • Patent number: 5360760
    Abstract: A vapor phase epitaxial growth method of a compound semiconductor is provided. On a semiconductor substrate held by a holder, a first epitaxial layer is grown using a first growth gas and then, a separator gas is emitted to the vicinity of the substrate to separate the substrate from the first growth gas. After the separator gas is removed from the vicinity, a second growth gas is supplied to the vicinity to form a second epitaxial layer on the first epitaxial layer. Since the substrate is separated by the separator gas from the first growth gas, transition regions of crystal composition and carrier concentration are difficult to be generated.
    Type: Grant
    Filed: March 30, 1993
    Date of Patent: November 1, 1994
    Assignee: NEC Corporation
    Inventor: Jun Hayashi
  • Patent number: 5352627
    Abstract: A process for fabricating sequential inductors and varactor diodes of a monolithic, high voltage, nonlinear, transmission line in GaAs is disclosed. An epitaxially grown laminate is produced by applying a low doped active n-type GaAs layer to an n-plus type GaAs substrate. A heavily doped p-type GaAs layer is applied to the active n-type layer and a heavily doped n-type GaAs layer is applied to the p-type layer. Ohmic contacts are applied to the heavily doped n-type layer where diodes are desired. Multiple layers are then either etched away or Oxygen ion implanted to isolate individual varactor diodes. An insulator is applied between the diodes and a conductive/inductive layer is thereafter applied on top of the insulator layer to complete the process.
    Type: Grant
    Filed: May 10, 1993
    Date of Patent: October 4, 1994
    Inventor: Gregory A. Cooper
  • Patent number: 5284783
    Abstract: A method of fabricating a semiconductor device having an epitaxial layer of a group III-V semiconductor material provided on an underlying crystal layer with a lattice matching therewith, the semiconductor material being doped to the p-type by addition of beryllium and selected from a group including gallium aluminum arsenide and indium gallium aluminum arsenide, in which the method comprises steps of growing the epitaxial layer on the underlying crystal layer, adding beryllium to a concentration level of about 5.times.10.sup.19 atoms/cm.sup.3 to about 5.times.10.sup.20 atoms/cm.sup.3 to the semiconductor material, and adding indium by an amount of about 0.5 mole percent to about 8 mole percent with respect to group III elements in the semiconductor material.
    Type: Grant
    Filed: July 2, 1991
    Date of Patent: February 8, 1994
    Assignee: Fujitsu Limited
    Inventors: Hideaki Ishikawa, Toshio Fujii, Eizo Miyauchi
  • Patent number: 5272106
    Abstract: Disclosed is a method for the making of an optoelectronic device such as buried lasers in which the different layers of the device are chiefly made during a single step of epitaxy by means of a removable mechanical mask.
    Type: Grant
    Filed: June 29, 1992
    Date of Patent: December 21, 1993
    Assignee: Thomson-CSF
    Inventors: Jean-Pierre Hirtz, Jean-Charles Garcia, Philippe Maurel
  • Patent number: 5268317
    Abstract: A method of making a MOS field effect transistor having shallow source and drain regions with improved breakdown and leakage characteristics includes the step of forming a layer of a metal silicide along a surface of a body of silicon at each side of a gate which is on an insulated from the surface. A high concentration of an impurity of a desired conductivity type is implanted only into the metal silicide layers. A lower concentration of the impurity is then implanted through the metal silicide layers and into the body just beneath the metal silicide layers. The body is then annealed at a temperature which drives the impurities from the metal silicide layer into the body to form the junctions.
    Type: Grant
    Filed: November 12, 1991
    Date of Patent: December 7, 1993
    Assignee: Siemens Aktiengesellschaft
    Inventors: Udo Schwalke, Christoph Zeller, Heinrich J. Zeininger, Wilfried Hansch
  • Patent number: 5256580
    Abstract: An optical semiconductor device is formed by using one controlled etch to form a "T" shaped contact structure on the device (20). The etch rate is controlled by judicious selection of materials to provide a cladding layer (17) that has a predetermined etch rate in hydrofluoric acid, a support layer (10) and a contact layer (18) that are not affected by hydrofluoric acid, a lift-off layer (19) that is dissolved by hydrofluoric acid, and a barrier layer (21). Dissolving of the lift-off layer (19) facilitates removing the barrier layer (21).
    Type: Grant
    Filed: April 6, 1992
    Date of Patent: October 26, 1993
    Assignee: Motorola, Inc.
    Inventors: Craig A. Gaw, Ronald W. Slocumb, Curtis D. Moyer
  • Patent number: 5238869
    Abstract: Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs (110) on silicon (102) is accomplished by formation of a defect annihilating grid (104) on the silicon (102) prior to the epitaxy of the GaAs (110).
    Type: Grant
    Filed: July 27, 1992
    Date of Patent: August 24, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Hisashi Shichijo, Richard J. Matyi
  • Patent number: 5232869
    Abstract: In the deposition of metal on solid substrates by a Metal Organic Chemical Deposition process, an improvement comprises the provision of vapors of a precursor of the metal by passing an inert carrier gas through a mixture of the metal precursor and a liquid having a vapor pressure at ambient temperature lower than that of the metal precursor and in which the metal precursor is at least partially soluble.
    Type: Grant
    Filed: July 28, 1992
    Date of Patent: August 3, 1993
    Assignee: Shell Research Limited
    Inventors: Dario M. Frigo, Antonius W. Gal
  • Patent number: 5230712
    Abstract: A method for making an electrochemical capacitor is disclosed. A plurality of bipolar electrodes having porous conductive oxide coatings on opposite sides of a thin metal foil are first produced in a fixture assembly using sol-gel processing techniques. A dielectric oxide coating is then applied to one or both conductive coatings using the sol-gel process. A stack of a plurality of the bipolar electrodes with adjacent electrodes separated by a predetermined amount of a solid electrolyte is assembled. The stacked assembly is heated to a temperature above the electrolyte melting point allowing the molten electrolyte to infiltrate the porous coatings. Pressure is applied to the stacked assembly sufficient to produce intimate contact between adjacent surfaces of the bipolar electrodes while expelling excess liquid from between the electrode surfaces. The stacked assembly is cooled in a controlled fashion to produce a laminate structure.
    Type: Grant
    Filed: September 28, 1992
    Date of Patent: July 27, 1993
    Inventor: M. Dean Matthews
  • Patent number: 5229320
    Abstract: Disclosed is a method which enabled the precise formation of a group of quantum dots. A device which functions on the principle of a transmission type electron microscope is used to produce a beam of electrons which are passed through a thin crystal membrane in order to produce an electron beam diffraction image. The energy distribution of the diffracted electron beam is used to produce masks, enable epitaxial growth and dry etching involved with the microscopic fabrication operations. For example, a thin GaAs membrane is used to form a diffracted electron beam image on a GaAs layer formed on a substrate. Carbon is then supplied and used to form carbon layers on the the locations where the beam energy is strongest. These carbon layers are used as a mask which allow selective etching of the GaAs layer.
    Type: Grant
    Filed: July 28, 1992
    Date of Patent: July 20, 1993
    Assignee: Sony Corporation
    Inventor: Ryuichi Ugajin
  • Patent number: 5225375
    Abstract: For plasma enhanced chemical vapor processing of semiconductor substrates, substrates are mounted on an elongate support, in a spaced parallel array. A shaft is rotatably mounted on the support and has electrode holding means, the electrodes alternating in polarity. The shaft, when rotated, moves the electrodes down in between the substrates, for positioning of the assembly in a reaction chamber for processing. After processing, and removal from the chamber, the shaft is rotated to move the electrodes out from between the substrates, to permit easy loading and unloading. The substrates are normally supported on boats positioned on the support. A particularly effective rf power feedthrough connects rf power from a power source through the door of the chamber.
    Type: Grant
    Filed: May 20, 1991
    Date of Patent: July 6, 1993
    Assignee: Process Technology (1988) Limited
    Inventors: Kamel Aite, R. B. DesBrisay, Lee Danisch
  • Patent number: 5223002
    Abstract: Highly conducting polyaniline is produced in situ in a tantalum capacitor by subjecting an excess of monomeric aniline to a solution having a low concentration of ammonium persulfate reagent. The monomer is oxidized by the reagent in preference to the polymer, so that the presence of excess monomer protects the polymer as it is produced against further oxidation to a less conductive species.
    Type: Grant
    Filed: October 31, 1991
    Date of Patent: June 29, 1993
    Assignee: Sprague Electric Company
    Inventor: Sidney D. Ross
  • Patent number: 5219786
    Abstract: A semiconductor layer annealing method comprises a step of heating a wafer consisting of a substrate and a semiconductor layer formed thereon by a heating means at a preheating temperature which will not exercise adverse thermal effect on the substrate, heating a portion of a small area of the semiconductor layer by a pulse of an excimer laser beam in one annealing cycle to a temperature higher than the preheating temperature and high enough to anneal the portion of the semiconductor layer, and repeating the annealing cycle to anneal the successive portions of the semiconductor layer sequentially.
    Type: Grant
    Filed: June 11, 1992
    Date of Patent: June 15, 1993
    Assignee: Sony Corporation
    Inventor: Takashi Noguchi