Patents Examined by Ramamohan Rao
-
Patent number: 5686355Abstract: A method for forming a film of refractory metal used for interconnection in a semiconductor integrated circuit and, above all, to a method for forming a tungsten film (Blk-W film) by a blanket CVD method. A blanket tungsten (Blk-W) film 10 is formed with good adherence and coverage on an SiO.sub.X based interlayer insulating film 3 having a minute-sized contact hole 4 for improving reliability in an interconnection. Before proceeding to Blk-W-CVD, a substrate having a Ti-based adherent layer 7 on its uppermost surface is heated and exposed to a silane-based gas atmosphere for forming Si-nuclei on its surface. A W-nucleus 9 is formed by reducing the WF.sub.6 gas with H.sub.2 and a Blk-W film 10 is also formed by reducing the WF.sub.6 with SiH.sub.4 under a rate determined by the rate of the surface reaction. If the substrate is preliminarily heated before forming the Si nuclei, formation of the Si nuclei proceeds with improved uniformity. The W-nuclei may be carried out uniformly in a temperature range of 450.Type: GrantFiled: October 23, 1995Date of Patent: November 11, 1997Assignee: Sony CorporationInventors: Hirofumi Sumi, Chigusa Yamane
-
Patent number: 5663090Abstract: An embodiment of the present discloses a thermal process for forming hemispherical grained silicon on a silicon material by the steps of: heating the silicon material to a steady state temperature; exposing the silicon material to a hydrogen containing ambient; and causing a decreasing temperature differential of the silicon material while exposing the silicon material to a silicon hydride gas. This embodiment is accomplished by using a thermal cycle having a temperature ramp up period, a temperature steady state period during at least a portion of which the H.sub.2 ambient is present and temperature ramp down period during at least a portion of which the diluted silicon hydride gas is present. A second embodiment discloses a process for forming a hemispherical grained silicon surface on at least one capacitor plate made of silicon material, by increasing the temperature of the capacitor plate in an H.sub.Type: GrantFiled: June 29, 1995Date of Patent: September 2, 1997Assignee: Micron Technology, Inc.Inventors: Charles H. Dennison, Randhir P. S. Thakur
-
Patent number: 5656540Abstract: On a surface of a p-type GaAs (111)B substrate 11, a mesa groove is formed along a [211]A direction. TDMAAs as a group V material and TMGa as a group III material are supplied at 8.times.10.sup.-3 Pa and 8.times.10.sup.-4 Pa, respectively, to grow n-type GaAs 13 dominantly on a side surface of a mesa 12. Subsequently, the group V material is changed to metal As. As.sub.4 and MAGa are supplied at 5.times.10.sup.-3 Pa and 8.times.10.sup.-4 Pa, respectively, to grow p-type GaAs 14 only on a side surface of the GaAs 13. Then, the group V material is again changed to TDMAAs. TDMAAs and TMGa are supplied both at 8.times.10.sup.-4 Pa to grow p-type GaAs 15.Type: GrantFiled: March 28, 1995Date of Patent: August 12, 1997Assignee: Optoelectronics Technology Research CorporationInventors: Yasuhiko Nomura, Shigeo Goto, Yoshitaka Morishita
-
Patent number: 5654230Abstract: A doped film forming method comprising, the steps of preparing gas source for supplying a film forming gas into the process tube, gas source for supplying doping gases, in which a dope is included, into the process tube, a dry pump for exhausting the process tube, and an apparatus for burning a not-reacted element in waste gas, arranging a plurality of substrates in the process tube in such a way that they are separated from their adjacent ones by a certain interval, exhausting the process tube to keep it reduced in pressure, heating the substrates in the process tube to a temperature range of 500.degree.-600.degree. C., controlling amounts of the doping and film forming gases, while exhausting the process tube, at the ratio of the amount of the film forming gas to the amount of the doping gases being in the range of 1 to 1.625.times.10.sup.-3 to 2.125.times.10.sup.-3, and causing the doping and film forming gases to be reacted with the substrates.Type: GrantFiled: April 7, 1995Date of Patent: August 5, 1997Assignees: Tokyo Electron Limited, Mitsubishi Denki Kabushiki KaishaInventors: Shinichi Jintate, Yoshihiko Okamoto, Toshiharu Nishimura, Atsushi Hosaka
-
Patent number: 5622900Abstract: A method of fabricating debris intolerant devices 30, and especially micro-mechanical devices such as DMDs, that allows wafers 22 to be sawn prior to completing all fabrication steps. Some devices are too fragile to allow cleaning operations to be performed after fabrication of the device. A solution is to saw and clean the wafers prior to completing the fabrication steps that make the device fragile. To prevent having to process the chips 30 individually, a substrate wafer 28 is attached to the backside of the dicing tape 24. This substrate wafer holds the sawn chips 30 in alignment allowing the remaining fabrication steps to be performed in wafer form.Type: GrantFiled: January 12, 1995Date of Patent: April 22, 1997Assignee: Texas Instruments IncorporatedInventor: Gregory C. Smith
-
Patent number: 5607876Abstract: The present invention consists of an electroluminescent structure and method of fabrication of that structure in materials which have an indirect bandgap in their bulk form. The processing steps can all be standard VLSI methods. Quantum columns, quantum wires or quantum dots may be formed, for example in an array, by masking, reactive ion etching and oxidation. When the semiconductor core is sufficiently thin, quantum mechanical confinement effects raise the energy and the radiative recombination efficiency of injected carriers. Tuning the core diameters allows selection of individual or multiple wavelength emission bands.Type: GrantFiled: December 29, 1995Date of Patent: March 4, 1997Assignee: Xerox CorporationInventors: David K. Biegelsen, Nicholas K. Sheridon, Noble M. Johnson
-
Patent number: 5580822Abstract: A starting gas feeding apparatus for forming a gaseous starting material from a liquid starting material and feeding the gaseous starting material into a reaction chamber of a CVD apparatus, comprises; a container that holds the liquid starting material, pressure reducing means for reducing the pressure inside the container, and heating means for heating the liquid starting material held in the container; the liquid starting material being boiled.Type: GrantFiled: May 25, 1995Date of Patent: December 3, 1996Assignee: Canon Kabushiki KaishaInventors: Yukihiro Hayakawa, Yasushi Kawasumi, Kenji Makino, Yuzo Kataoka
-
Patent number: 5534459Abstract: Method for forming an SOI (Silicon On Insulator) structured substrate comprising the steps of forming a first insulation film on a silicon substrate, selectively exposing the substrate by selectively removing the first insulation film, forming high density impurity regions in the substrate by injecting high density impurity ions into the exposed substrate wherefrom the first insulation film has been removed, forming a first epitaxial layer on the surface of the first insulation film and the high density impurity regions, removing a portion of the first epitaxial layer on each of the high density impurity regions, forming a second insulation film on the first epitaxial layer, forming an insulation layer including the first insulation film and the second insulation film on the substrate by etching the second insulation film to expose the first epitaxial layer, and growing a second epitaxial layer on the surface of the insulation layer.Type: GrantFiled: June 7, 1995Date of Patent: July 9, 1996Assignee: LG Semicon Co., Ltd.Inventor: Sung S. Kim
-
Patent number: 5529640Abstract: In one form of the invention, a method for the growth of an epitaxial insulator-metal structure on a semiconductor surface comprising the steps of maintaining the semiconductor surface at a pressure below approximately 1.times.10.sup.-7 mbar, maintaining the semiconductor surface at a substantially fixed first temperature between approximately 25.degree. C. and 400.degree. C., depositing an epitaxial metal layer on the semiconductor surface, adjusting the semiconductor surface to a substantially fixed second temperature between approximately 25.degree. C. and 200.degree. C., starting a deposition of epitaxial CaF.sub.2 on the first metal layer, ramping the second temperature to a third substantially fixed temperature between 200.degree. C. and 500.degree. C. over a time period, maintaining the third temperature until the epitaxial CaF.sub.2 has deposited to a desired thickness, and stopping the deposition of epitaxial CaF.sub.2 on the first metal layer.Type: GrantFiled: September 8, 1994Date of Patent: June 25, 1996Assignee: Texas Instruments IncorporatedInventor: Chih-Chen Cho
-
Patent number: 5525159Abstract: A plasma CVD apparatus for forming a silicon film on an LCD substrate includes a container which is divided into process and upper chambers by a quartz partition plate. A work table on which the substrate is mounted is arranged in the process chamber and a lower electrode to which a high frequency potential is applied is arranged in the work table. First lower and second upper supply heads are arranged between the partition plate and the work table in the process chamber. SiH.sub.4 and H.sub.2 gas and He gases are supplied through the first and second supply heads. He gas is transformed into plasma while SiH.sub.4 and H.sub.2 gas is excited and decomposed by the plasma thus formed. Two coils are arranged in the upper chamber and high frequency voltages are applied to the coils to generate electromagnetic field to induce the transforming of He gas into plasma.Type: GrantFiled: December 16, 1994Date of Patent: June 11, 1996Assignee: Tokyo Electron LimitedInventors: Kiichi Hama, Jiro Hata, Toshiaki Hongoh
-
Patent number: 5506170Abstract: A semiconductor laser with a self-sustained pulsation is disclosed in which a first cladding layer of first conductive type, an active layer and a second cladding layer of second conductive type having a striped ridge are formed in that order on a semiconductor substrate of first conductive type. The first and second cladding layers have a refractive index smaller than and a band gap larger than the active layer. A saturable optical absorbing layer having a band gap of energy substantially equal to the energy corresponding to lasing wavelength is formed in both the first and second cladding layers. Further, a barrier layer having a refractive index smaller than and a band gap larger than the first and second cladding layers is formed between the first cladding layer and the active layer and/or between the active layer and the second cladding layer.Type: GrantFiled: December 28, 1994Date of Patent: April 9, 1996Assignee: Sanyo Electric Co., Ltd.Inventors: Keiichi Yodoshi, Akira Ibaraki, Masayuki Shono, Shoji Honda, Takatoshi Ikegami, Nobuhiko Hayashi, Koutarou Furusawa, Atushi Tajiri, Toru Ishikawa, Kenichi Matsukawa, Teruaki Miyake, Takenori Goto, Mitsuaki Matsumoto, Daisuke Ide, Yasuyuki Bessho
-
Patent number: 5500389Abstract: A process for formation of a hetero junction structured film utilizing V grooves is disclosed. A monocrystalline film 1 is etched into V grooves, and thereupon, a hetero film 2 having misfits is grown, so that dislocations would be intensively distributed within the V grooves. Then, an oxide layer 3 is formed thereupon, and then, the portions of the oxide layer 3 and the hereto film 2 corresponding to the V grooves are removed by carrying out an etching. Then, the residue oxide layer is removed, thereby forming a non-stress non-dislocation hetero junction structure. Further, the following steps can be added. That is, on the above structure, a thin oxide layer 3 is deposited by carrying out a thermal oxidation or a chemical deposition, and then, a polycrystalline silicon film 4 is deposited. Then the surface irregularities are smoothened by carrying out a selective grinding. Or the following steps may be added.Type: GrantFiled: November 17, 1994Date of Patent: March 19, 1996Assignee: Electronics & Telecommunications Research InstituteInventors: Seung-Chang Lee, Sun-Jin Yun, Bo-Woo Kim, Sang-Won Kang
-
Patent number: 5489549Abstract: High speed Group III-Sb materials are n-doped in a molecular beam epitaxy process by forming a superlattice with n-doped strained layers of a Group III-V compound upon Group III-Sb base layers. The base layers have lower conduction band energy levels than the strained layers, and allow doping electrons from the strained layers to flow into the base layers. The base layers preferably comprise Al.sub.x Ga.sub.1-x Sb, while the strained layers preferably comprise a binary or ternary compound such as Al.sub.y Ga.sub.1-y As having a single Group V component, where x and y are each from 0 to 1.0. The strained layers can be n-doped with silicon or tin, which would produce p-type doping if added directly to the base layers.Type: GrantFiled: April 14, 1994Date of Patent: February 6, 1996Assignee: Hughes Aircraft CompanyInventors: Thomas C. Hasenberg, April S. Brown, Lawrence E. Larson
-
Patent number: 5484736Abstract: A process for producing a cadmium telluride polycrystalline film having grain sizes greater than about 20 .mu.m. The process comprises providing a substrate upon which cadmium telluride can be deposited and placing that substrate within a vacuum chamber containing a cadmium telluride effusion cell. A polycrystalline film is then deposited on the substrate through the steps of evacuating the vacuum chamber to a pressure of at least 10.sup.-6 torr.; heating the effusion cell to a temperature whereat the cell releases stoichiometric amounts of cadmium telluride usable as a molecular beam source for growth of grains on the substrate; heating the substrate to a temperature whereat a stoichiometric film of cadmium telluride can be deposited; and releasing cadmium telluride from the effusion cell for deposition as a film on the substrate.Type: GrantFiled: September 19, 1994Date of Patent: January 16, 1996Assignee: Midwest Research InstituteInventors: Falah S. Hasoon, Art J. Nelson
-
Patent number: 5474954Abstract: A manufacturing method of a semiconductor laser diode is disclosed in which a current cutoff layer is formed on the wall of a first metal layer by a low-temperature process such as plasma-enhanced chemical vapor deposition and the gas composition ratio of the reactive ion etching process is appropriately controlled so that the maximum area can be secured for a self-aligned first metal exposing area, i.e., an ohmic contact area. This minimizes the generation of heat during lasing and enhances reliability. Further, the present invention stabilizes the process by self alignment.Type: GrantFiled: October 21, 1994Date of Patent: December 12, 1995Assignee: Samsung Electronics Co., Ltd.Inventor: Seung-kee Yang
-
Patent number: 5453399Abstract: In one form of the invention, a method is disclosed for fabricating a semiconductor-on-insulator structure comprising the steps of: forming an insulator layer 22; forming a layer 24 comprising boron (B) on the insulator layer 22; and forming a semiconductor layer 26 on the layer 24 comprising B.Type: GrantFiled: October 6, 1993Date of Patent: September 26, 1995Assignee: Texas Instruments IncorporatedInventor: Chih-Chen Cho
-
Patent number: 5439843Abstract: A semiconductor substrate comprises an insulating layer and a compound semiconductor monocrystal thin film formed on said insulating layer, the thermal expansion coefficient of said insulating layer being in the range of 60%-140% of that of said monocrystal thin film.Type: GrantFiled: September 6, 1994Date of Patent: August 8, 1995Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Takao Yonehara, Mamoru Miyawaki
-
Patent number: 5434101Abstract: In the manufacture of a single crystal film by epitaxial growth method, defects such as cracking are avoided by increasing the deviation of the lattice constant of the resulting film in the direction of growth from the substrate. Preferably, the deviation is increased at the rate of (0.4.about.9).times.10.sup.-4 %/.mu.m.Type: GrantFiled: March 2, 1993Date of Patent: July 18, 1995Assignee: TDK CorporationInventors: Kazuhito Yamasawa, Atsushi Oido, Akio Nakata, Nobuya Uchida
-
Patent number: 5431735Abstract: A phosphorus effusion cell for molecular beam epitaxy is disclosed. It consists of a vessel in which, by sublimation of red phosphorus, the vapor of this element is produced, the vessel being closed by means of a vacuum tight valve which regulates its flow. In the vessel, there are two zones having different temperatures, one of sublimation of red phosphorus and another of condensation and re-evaporation of white phosphorus, both zones being thermally insulated by means of reflecting screens which prevent the temperature of the heating resistance from having to reach temperatures above 350.degree. C. The valve, intermittent closing of which regulates the effusion of phosphorus vapor, is at a temperature slightly above that of the thermostated zone of condensation/re-evaporation of the white phosphorus. It finds applicable in the manufacture of semiconducting structures.Type: GrantFiled: January 14, 1994Date of Patent: July 11, 1995Assignee: Riber S.A.Inventor: Fernando F. Briones
-
Patent number: 5432122Abstract: The present invention provides a method of making a thin film transistor for driving a liquid crystal display comprising the steps of forming a gate electrode on a glass substrate and forming an insulating layer and an amorphous silicon layer in turn on said glass substrate and said gate electrode, and scanning laser beams on the surface of said amorphous silicon layer with the end portions of the respective scanned laser beams being overlapped. According to the method of making a thin film transistor for driving a liquid crystal display of the present invention, a thin film transistor suitable for HDTV, the field effect mobility of which is high, is achieved. Further, in making a thin film transistor, a separate processing step is not required and the number of processing steps can be reduced because constructional features of a TFT are utilized.Type: GrantFiled: November 3, 1993Date of Patent: July 11, 1995Assignee: Gold Star Co., Ltd.Inventor: Kie S. Chae