Patents Examined by Ramamohan Rao
  • Patent number: 5658824
    Abstract: A semiconductor laser device includes: a lower cladding layer; an upper cladding layer having a bottom and a strip-shaped ridge portion projecting from the bottom; a II-VI compound semiconductor active layer interposed between the lower cladding layer and the upper cladding layer; and a burying blocking layer made of an aromatic polyamide resin formed on a bottom of the upper cladding layer so as to be in contact with sides of the stripe-shaped ridge portion.
    Type: Grant
    Filed: August 31, 1995
    Date of Patent: August 19, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigetoshi Itoh, Toshiyuki Okumura
  • Patent number: 5656531
    Abstract: An embodiment of the present invention develops a process for forming Hemi-Spherical Grained silicon by the steps of: forming amorphous silicon from a gas source comprising at least one of dichlorosilane, disilane or trisilane, wherein the amorphous silicon comprising at least one impurity doped amorphous portion, the amorphous silicon is deposited at a deposition temperature no greater than 525.degree. C; and annealing the amorphous silicon for a sufficient amount of time and at an elevated annealing temperature, thereby transforming the amorphous silicon into the Hemi-Spherical Grained silicon.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: August 12, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, Lyle D. Breiner
  • Patent number: 5656540
    Abstract: On a surface of a p-type GaAs (111)B substrate 11, a mesa groove is formed along a [211]A direction. TDMAAs as a group V material and TMGa as a group III material are supplied at 8.times.10.sup.-3 Pa and 8.times.10.sup.-4 Pa, respectively, to grow n-type GaAs 13 dominantly on a side surface of a mesa 12. Subsequently, the group V material is changed to metal As. As.sub.4 and MAGa are supplied at 5.times.10.sup.-3 Pa and 8.times.10.sup.-4 Pa, respectively, to grow p-type GaAs 14 only on a side surface of the GaAs 13. Then, the group V material is again changed to TDMAAs. TDMAAs and TMGa are supplied both at 8.times.10.sup.-4 Pa to grow p-type GaAs 15.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: August 12, 1997
    Assignee: Optoelectronics Technology Research Corporation
    Inventors: Yasuhiko Nomura, Shigeo Goto, Yoshitaka Morishita
  • Patent number: 5654230
    Abstract: A doped film forming method comprising, the steps of preparing gas source for supplying a film forming gas into the process tube, gas source for supplying doping gases, in which a dope is included, into the process tube, a dry pump for exhausting the process tube, and an apparatus for burning a not-reacted element in waste gas, arranging a plurality of substrates in the process tube in such a way that they are separated from their adjacent ones by a certain interval, exhausting the process tube to keep it reduced in pressure, heating the substrates in the process tube to a temperature range of 500.degree.-600.degree. C., controlling amounts of the doping and film forming gases, while exhausting the process tube, at the ratio of the amount of the film forming gas to the amount of the doping gases being in the range of 1 to 1.625.times.10.sup.-3 to 2.125.times.10.sup.-3, and causing the doping and film forming gases to be reacted with the substrates.
    Type: Grant
    Filed: April 7, 1995
    Date of Patent: August 5, 1997
    Assignees: Tokyo Electron Limited, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinichi Jintate, Yoshihiko Okamoto, Toshiharu Nishimura, Atsushi Hosaka
  • Patent number: 5654229
    Abstract: A method for providing an nonlinear, frequency converting optical QPM waveguide device by growing a first ferroelectric oxide film or layer on a second ferroelectric layer or medium wherein, in first and second embodiments, respectively, the second layer is initially provided with a periodic nonlinear coefficient pattern or a periodic pattern comprising a seed layer. During the growth of the first layer, the periodic pattern formed in the second layer, is replicated, transformed or induced into the first layer resulting in a plurality of substantially rectangular prismatic-shaped domains in the first layer having the periodic nonlinear coefficient pattern status based upon the periodic patterning of the second layer.
    Type: Grant
    Filed: April 26, 1995
    Date of Patent: August 5, 1997
    Assignee: Xerox Corporation
    Inventors: Florence E. Leplingard, John J. Kingston, Ross D. Bringans, David K. Fork, Robert G. Waarts, David F. Welch, Randall S. Geels
  • Patent number: 5652178
    Abstract: A method of manufacturing a light emitting diode, which includes the steps of bringing a semiconductor substrate of p-type or n-type into contact with a growth solution at a high temperature and thereafter, lowering the temperature so as to form a monocrystalline epitaxial layer of the same type as the semiconductor substrate on the semiconductor substrate, subsequently, further lowering the above temperature to form a first monocrystalline epitaxial layer of a reverse type to the epitaxial layer on the epitaxial layer and then, cutting off the growth solution to form an epitaxial wafer as a result, a growth solution to contact the first epitaxial layer of a epitaxial wafer at a high temperature, and thereafter, the temperature is lowered to form a second monocrystalline epitaxial layer of the same kind and type as the first epitaxial layer on the first epitaxial layer.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: July 29, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tadasu Izumi, Masamichi Harada, Yukari Inoguchi
  • Patent number: 5648295
    Abstract: A semiconductor laser device in which semiconductor layers of an n-type cladding layer, a quantum well active layer 106, a p-type cladding layer, and an intermediate layer are formed on an n-type GaAs substrate in successive order, and a mixed-crystal is formed in a region except the semiconductor layers of the contact layer and the lower part of the contact layer by diffusing Si into the structure from above the intermediate layer, characterized in that the contact layer and the intermediate layer are made of n-type or nonconductive semiconductor material, and a p-type low-resistance region, formed by diffusing Zn into the structure from above the contact layer, is profiled so as not to overlap with the mixed-crystal region formed by Si diffusion.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: July 15, 1997
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Hiromi Otoma, Nobuaki Ueki, Hideki Fukunaga, Hideo Nakayama, Yasuji Seko, Mario Fuse
  • Patent number: 5647917
    Abstract: When compound semiconductor films are grown on an InP wafer having a surface near a (100) orientation hillocks tend to arise on the films. Off-angle wafers have been adopted for substrates in order to suppress the occurrence of hillocks. The off-angle .THETA. from a (100) plane, however, is not the sole factor for determing wheather hillocks will be formed on the film. There is a concealed parameter which determines the generation of hillocks. What induces hillocks on the growing film are the defects on the substrate itself. No hillocks originate on portions of the film that correspond to the portions of the InP wafer without dislocations. The role of the off-angle .THETA. of the substrate is preventing the influence of the dislocations from transmitting to the films. A smaller density D of the defects on the substrate allows a smaller off-angle .THETA. for suppressing the hillocks from arising.
    Type: Grant
    Filed: September 7, 1995
    Date of Patent: July 15, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiko Oida, Ryusuke Nakai
  • Patent number: 5643828
    Abstract: A method of manufacturing a quantum device such as a coupled quantum boxes device are disclosed. The quantum device comprises: a semiconductor substrate; a plurality of box portions made of a first semiconductor; and a layer made of a second semiconductor provided on circumferences of the box portions, a plurality of quantum boxes being provided with the box portions and the layer of the second semiconductor. The manufacturing method comprises the steps of: making a plurality of box portions of a first semiconductor on a semiconductor substrate; and covering circumferences of the box portions with a layer of a second semiconductor, a plurality of quantum boxes being provided with the box portions and the layer of the second semiconductor.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: July 1, 1997
    Assignee: Sony Corporation
    Inventors: Ryuichi Ugajin, Ichiro Hase, Kazumasa Nomoto
  • Patent number: 5639685
    Abstract: A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate includes, a) providing a layer of conductively doped silicon over the substrate to a thickness greater than about 200 Angstroms; b) depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer to a thickness of from 100 Angstroms to about 400 Angstroms; c) positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; d) with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; e) with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; f) with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 2
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: June 17, 1997
    Assignee: Micron Technology, Inc.
    Inventors: John K. Zahurak, Klaus F. Schuegraf, Randhir P. S. Thakur
  • Patent number: 5637531
    Abstract: A process for fabricating a multilayer crystalline structure of nitrides of metals from group III of periodic table including GaN, AlN and InN is provided. The process includes the steps of heating a group III metal (26) to a temperature T1 under an equilibrium nitrogen pressure while maintaining group III metal nitride stability to form a first crystal layer of the group III metal nitride. Thereafter the method includes the step of forming a second crystal layer (28) of the group III metal nitride by decreasing the nitrogen pressure such that the second crystal layer grows on the first layer with a growth rate slower than the growth rate of the first layer at a temperature T2 not greater than temperature T1. The second layer (28) grows on at least a portion of the first layer at a predetermined thickness under the new nitrogen pressure.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: June 10, 1997
    Assignee: High Pressure Research Center, Polish Academy
    Inventors: Sylwester Porowski, Jan Jun, Izabella Grzegory, Stanislaw Krukowski, Miroslaw Wroblewski
  • Patent number: 5633192
    Abstract: An epitaxial growth system comprises a housing around an epitaxial growth chamber. A substrate support is located within the growth chamber. A gallium source introduces gallium into the growth chamber and directs the gallium towards the substrate. An activated nitrogen source introduces activated nitrogen into the growth chamber and directs the activated nitrogen towards the substrate. The activated nitrogen comprises ionic nitrogen species and atomic nitrogen species. An external magnet and/or an exit aperture control the amount of atomic nitrogen species and ionic nitrogen species reaching the substrate.
    Type: Grant
    Filed: January 13, 1995
    Date of Patent: May 27, 1997
    Assignee: Boston University
    Inventors: Theodore D. Moustakas, Richard J. Molnar
  • Patent number: 5633193
    Abstract: Heteroepitaxial growth of phosphorus-containing III/V semiconductor material (e.g., InGaAsP) on a non-planar surface of a different phosphorus-containing III/V semiconductor material (e.g., InP) is facilitated by heating the non-planar surface in a substantially evacuated chamber to a mass-transport temperature, and exposing the surface to a flux of at least phosphorus form a solid phosphorus source. This mass-transport step is followed by in situ growth of the desired semiconductor material, with at least an initial portion of the growth being done at a first growth temperature that is not greater than the mass transport temperature. Growth typically is completed at a second growth temperature higher than the first growth temperature. A significant aspect of the method is provision of the required fluxes (e.g., phosphorus, arsenic, indium, gallium) from solid sources, resulting in hydrogen-free mass transport and growth, which can be carried out at lower temperatures than is customary in the prior art.
    Type: Grant
    Filed: May 22, 1996
    Date of Patent: May 27, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: James N. Baillargeon, Alfred Y. Cho, Sung-Nee G. Chu, Wen-Yen Hwang
  • Patent number: 5633194
    Abstract: A low temperature ion-beam assisted deposition process, comprising the steps of cleaning at least one substrate, subjecting the substrate to a vacuum of at least 2.times.10.sup.-4 Torr, heating the substrate to a temperature of at least 280.degree. C., and directing an ion beam at the substrate, wherein the ion beam comprises ion-associated gas molecules of Si or Ge, so as to grow a thin epitaxial film of Si or Ge on the substrate.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: May 27, 1997
    Assignee: The University of Waterloo
    Inventors: C. R. Selvakumar, S. Mohajerzadeh, D. E. Brodie
  • Patent number: 5629223
    Abstract: The present invention develops a process for forming hemi-spherical grained silicon storage capacitor plates by the steps of: forming a silicon layer over a pair of neighboring parallel conductive lines, the silicon layer making contact to an underlying conductive region; patterning the silicon layer to form individual silicon capacitor plates; exposing the silicon capacitor plates to a fluorine based gas mixture during an high vacuum annealing period, thereby transforming the silicon capacitor plates into the semi-spherical grained silicon capacitor plates; conductively doping the hemi-spherical grained silicon capacitor plates; forming a capacitor dielectric layer adjacent and coextensive the semi-spherical grained silicon capacitor plates; and forming a second conductive silicon layer superjacent and coextensive the capacitor dielectric layer.
    Type: Grant
    Filed: November 15, 1994
    Date of Patent: May 13, 1997
    Assignee: Micron Technology, Inc.
    Inventor: Randhir P. S. Thakur
  • Patent number: 5627100
    Abstract: A method for making a set of surface-emitting laser diodes comprises the making of reflectors by the epitaxial growth of at least one semiconductor material through a mask having apertures with inclined flanks. This method leads to the obtaining of the Bragg reflectors obtained in situ, removing the need for the ion etching of a semiconductor substrate followed by a phase for the conditioning of the surface of the sample before the preparation of the desired laser structure.Application: optical power source.
    Type: Grant
    Filed: September 7, 1995
    Date of Patent: May 6, 1997
    Assignee: Thomson-CSF
    Inventors: Philippe Maurel, Jean-Charles Garcia, Jean-Pierre Hirtz
  • Patent number: 5627088
    Abstract: A photoelectric conversion device having a photoelectric conversion section and a transistor for transferring or amplification of the photoelectric conversion signal or an accumulating section of a photo carrier. The photoelectric conversion section and the transistor or the accumulating section have common semiconductor layer.
    Type: Grant
    Filed: September 29, 1993
    Date of Patent: May 6, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masaki Fukaya, Soichiro Kawakami, Satoshi Itabashi, Katsunori Terada, Ihachiro Gofuku, Katsumi Nakagawa, Katsunori Hatanaka, Yoshinori Isobe, Toshihiro Saika, Tetsuya Kaneko, Nobuko Kitahara, Hideyuki Suzuki
  • Patent number: 5622900
    Abstract: A method of fabricating debris intolerant devices 30, and especially micro-mechanical devices such as DMDs, that allows wafers 22 to be sawn prior to completing all fabrication steps. Some devices are too fragile to allow cleaning operations to be performed after fabrication of the device. A solution is to saw and clean the wafers prior to completing the fabrication steps that make the device fragile. To prevent having to process the chips 30 individually, a substrate wafer 28 is attached to the backside of the dicing tape 24. This substrate wafer holds the sawn chips 30 in alignment allowing the remaining fabrication steps to be performed in wafer form.
    Type: Grant
    Filed: January 12, 1995
    Date of Patent: April 22, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Gregory C. Smith
  • Patent number: 5616514
    Abstract: A micromechanical sensor includes a support of silicon substrate having an epitaxial layer of silicon applied on the silicon substrate. A part of the epitaxial layer is laid bare to form at least one micromechanical deflection part by an etching process. The bared deflection part is made of polycrystalline silicon which has grown in polycrystalline form during the epitaxial process over a silicon-oxide layer which has been removed by etching. In the support region and/or at the connection to the silicon substrate, the exposed deflection part passes into single crystal silicon. By large layer thicknesses, a large working capacity of the sensor is possible. The sensor structure provides enhanced mechanical stability, processability, and possibilities of shaping, and it can be integrated, in particular, in a bipolar process or mixed process (bipolar-CMOS, bipolar-CMOS-DMOS).
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: April 1, 1997
    Assignee: Robert Bosch GmbH
    Inventors: Joerg Muchow, Horst Muenzel, Michael Offenberg, Winfried Waldvogel
  • Patent number: 5612250
    Abstract: A method for manufacturing a thin film transistor having a crystalline silicon layer as an active layer comprises the steps of disposing a solution containing a catalyst for promoting a crystallization of silicon in contact with an amorphous silicon film, crystallizing the amorphous silicon at a relatively low temperature and then improving the crystallinity by irradiating the film with a laser light. The concentration of the catalyst in the crystallized silicon film can be controlled by controlling the concentration of the catalyst in the solution.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 18, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Hongyong Zhang, Naoaki Yamaguchi, Atsunori Suzuki