Patents Examined by Ramon A Mercado
  • Patent number: 11886741
    Abstract: A method for reading data in a storage device is provided. The method includes receiving a read command from a host device, wherein the read command indicates stored data in the storage device and a Logical Block Address (LBA) of the stored data; obtaining a Physical Block Number (PBN) based on the LBA and a Logical to Physical (L2P) mapping; determining whether the PBN corresponds to a volatile memory of the storage device; reading the stored data directly from the volatile memory based on the PBN corresponding to the volatile memory; incrementing a read counter associated with the PBN based on the stored data being read directly from the volatile memory; and reading the stored data from a non-volatile memory of the storage device based on the PBN not corresponding to the volatile memory.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tushar Tukaram Patil, Anantha Sharma, Sharath Kumar Kodase
  • Patent number: 11868652
    Abstract: Disclosed is a method of allocating a buffer memory to a plurality of data storage zones. In some implementations, the method may include comparing a free buffer space size to a reallocation threshold size that is re-allocable at a reallocation cycle, deallocating, upon a determination that the free buffer space size is smaller than the reallocation threshold size, at least a portion of an occupied buffer space size to create a new free buffer space based on a history of buffer memory utilization of the occupied buffer space, and allocating the existing free buffer space and the new free buffer space to targeted data storage zones based on history of buffer memory utilizations corresponding to the targeted data storage zones.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: January 9, 2024
    Assignee: SK HYNIX INC.
    Inventor: Seong Won Shin
  • Patent number: 11868636
    Abstract: Prioritizing garbage collection based on the extent to which data is deduplicated, including: determining, for one or more data elements, a number of deduplicated references to each data element; storing, for each of the data elements, the data element in an area of the storage device that contains other data elements with a similar number of deduplicated references; and adjusting a garbage collection schedule for the storage device, wherein garbage collection operations are performed more frequently on areas of the storage device that contain data elements with a relatively low number of deduplicated references.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: January 9, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Ethan Miller, John Colgrove
  • Patent number: 11861224
    Abstract: The present disclosure generally relates to efficient data transfer. Rather than processing each command, the data storage device fetches part of the host buffers and then makes a determination regarding the attributes of the fetched buffers. Upon the determination, the command is classified as optimized, not-optimized, or somewhere in between. Optimized commands are permitted to retrieve data out of order while non-optimized commands remain in a strict in order data retrieval process. In between commands can be processed with some out of order data retrieval. In so doing, data transfers are effectively managed and optimized data by taking into account the current attributes of the host buffers per command.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: January 2, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 11860774
    Abstract: An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangkwon Moon, Kyung Ho Kim, Seunguk Shin, Sung Won Jung
  • Patent number: 11829629
    Abstract: Synchronous replication between storage systems with virtualized storage includes: assigning a virtual volume datastore to a pod, the pod including a management object, the virtual volume datastore including virtual machine data; stretching the pod from a first storage system to a second storage system, including copying the virtual machine data from the first storage system to the second storage system; and synchronously replicating access operations of the virtual machine data of the pod between the first and second storage systems.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: November 28, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Daniel Doucette, Cody Hosterman, John Colgrove, Neale Genereux
  • Patent number: 11789648
    Abstract: The invention introduces a method for configuring a reliable command, performed by a flash controller, including: issuing a read ID command to a flash module; and parsing an opcode of a reliable command from reserved bytes in reply data for the read ID command, where the reliable command is used to direct the flash module for access to data in a single level cell (SLC) mode.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: October 17, 2023
    Assignee: SILICON MOTION, INC.
    Inventor: Po-Wei Wu
  • Patent number: 11775206
    Abstract: A hardware unit for manipulating data stored in a memory comprises an internal buffer, a memory reading block, configured to read the data from the memory and write the data to the internal buffer. a memory writing block, configured to read the data from the internal buffer and write the data to the memory. The hardware unit optionally also comprises a control channel between the memory reading block and the memory writing block, wherein the memory reading block and the memory writing block are configured to communicate via the control channel to maintain synchronisation between them when writing the data to the internal buffer and reading the data from the internal buffer, respectively. The hardware unit may be configured to apply one or more transformations to multidimensional data in the memory. The hardware unit may be configured to traverse the multidimensional array using a plurality of nested loops.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: October 3, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Alan Vines, Stephen Spain, Fernando Escobar
  • Patent number: 11774989
    Abstract: A pulse shot-type flow rate control device including first and second shutoff valves, a tank, a pressure sensor, and a controller is caused to perform two or more processes. In each process, the controller repeats pulse shots of alternately causing the first shutoff valve and the second shutoff valve to open and close, changes a way of the pulse shots based on a pressure difference between the pressure after filling and the pressure after discharge, and controls a volume flow rate. In each process, the controller stores, as an optimal filling time, a filling time when the volume flow rate is controlled to a target flow rate, and opens and closes the first shutoff valve by using the optimal filling time in a first pulse shot in the next process.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: October 3, 2023
    Assignee: CKD CORPORATION
    Inventors: Hiroki Kadoya, Yasunori Nishimura
  • Patent number: 11762565
    Abstract: Apparatus and methods are disclosed, including a controller circuit, a volatile memory, a non-volatile memory, and a reset circuit, where the reset circuit is configured to receive a reset signal from a host device and actuate a timer circuit. The timer circuit, where the timer circuit is configured to cause a storage device to reset after a threshold time period. The reset circuit is further configured to actuate the controller circuit to write data stored in the volatile memory to the non-volatile memory before the storage device is reset.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Patent number: 11755476
    Abstract: A memory controller includes a buffer memory configured to store first meta data and second meta data having a different type from the first meta data, and a cache memory including first and second dedicated areas. The first meta data is cached in the first dedicated area and the second meta data is cached in the second dedicated area.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: September 12, 2023
    Assignee: SK hynix Inc.
    Inventors: Gi Jo Jeong, Do Hun Kim, Kwang Sun Lee
  • Patent number: 11733887
    Abstract: A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: August 22, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Luigi Pilolli, Ali Feiz Zarrin Ghalam, Guan Wang, Qiang Tang
  • Patent number: 11726690
    Abstract: A memory device includes a memory array comprising a first number of planes, a second number of independent plane driver circuits, wherein the second number is less than the first number, and a plane selection circuit to couple the second number of independent plane driver circuits to the first number of planes of the memory array. The memory device further includes control logic, to perform receive a first read command and identify, among the first number of planes, a first plane to which the first read command is directed. The control logic further configures the plane selection circuit to couple a first independent plane driver of the second number of independent plane drivers to the first plane and causes the first independent plane driver to perform a first read operation corresponding to the first read command on the first plane.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Theodore T. Pekny
  • Patent number: 11714732
    Abstract: Sets of asynchronous replication operations may be tracked to ensure consistency. A tracking service may receive notifications of pending asynchronous replication tasks, and responsive to receiving a manifest indicating a request to be notified upon completion of a set of pending replication asynchronous tasks, matches individual ones of the tasks within the set to tasks indicated as pending. The tracking service may then select a routing table based on a most recent sequence number associated with the set of tasks, determine one of more tracking nodes assigned to track the set of tasks, and send the manifest to each of the tracking nodes. As individual ones of the tasks complete, notifications of completion may be sent to the tracking nodes and an aggregator node aggregates the completion notifications for the set. Once all completion notifications are received, a response to the request indicating completion may be sent.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: August 1, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Jacob Wires, Julien Mascart, Valeri Atamaniouk, Jun Dai, Sidharth Bajaj, Wesley Shawn Davis
  • Patent number: 11709628
    Abstract: In file storage, a CPU is configured to: divide a file into a plurality of chunks, execute encoding processing on at least one of the chunks to obtain an encoded chunk, and store in cloud storage a plurality of chunks of the file including the encoded chunk; acquire, when receiving a read command of which target is data of a part of a file stored in the cloud storage, a read target chunk including data, which is a target of the read command, from the cloud storage; and execute, when an encoded chunk is included in the read target chunk, decoding processing on the encoded chunk, identify data that is a read target from the read target chunk including the chunk having been subjected to decoding processing, and hand over the identified data to a command source of the read command.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: July 25, 2023
    Assignee: HITACHI, LTD.
    Inventor: Tomoki Shimizu
  • Patent number: 11704067
    Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: July 18, 2023
    Assignee: NVIDIA Corporation
    Inventors: Ching-Yu Hung, Ravi P. Singh, Jagadeesh Sankaran, Ahmad Itani, Yen-Te Shih
  • Patent number: 11704240
    Abstract: A garbage data scrubbing method includes obtaining an input/output (IO) busy/idle status of a terminal at a current moment, where the IO busy/idle status includes a busy state and an idle state. When the IO busy/idle status of the terminal at the current moment is the idle state, a discard message is delivered to a storage device, where the discard message includes an initial address and a size of to-be-scrubbed physical space in the storage device, and where the discard message is used to unbind a mapping relationship between a physical address of the to-be-scrubbed physical space and a corresponding logical address.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: July 18, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chao Yu, Hao Chen, Bifeng Tong, Chengliang Zheng, Xiyu Zhou
  • Patent number: 11693772
    Abstract: A system and a method are disclosed that efficiently supports an append operation in an object storage system. A size of data received with a request for an append operation from an application is determined based on a data-alignment characteristic of a storage medium. Data that is not aligned with the data-alignment characteristic is stored in persistent memory and aggregated with other data from the application that is not aligned with the data-alignment characteristic, while data that is aligned with the data-alignment characteristic is stored directly in the storage medium. Aggregated data that becomes aligned with the data-alignment characteristic as additional requests for append operations are received are migrated to the storage medium.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: July 4, 2023
    Inventors: Angel Benedicto Aviles, Jr., Vinod Kumar Daga, Vamsikrishna Sadhu, Venkata Bhanu Prakash Gollapudi, Vijaya Kumar Jakkula
  • Patent number: 11693589
    Abstract: A storage device capable of maintaining consistency of data for the same address may include a memory device including a plurality of memory blocks, a buffer memory device including a plurality of cache buffers temporarily storing data previously received from a host, and a memory controller configured to receive a write request and a write data from the host and configured to control the buffer memory device and the memory device to store a previously received data, stored in one of the plurality of cache buffers with a logical address that matches a logical address of the write data, in the memory device before the write request is processed.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: July 4, 2023
    Assignee: SK hynix Inc.
    Inventor: Gi Pyo Um
  • Patent number: 11662909
    Abstract: A system and method for efficiently maintaining metadata stored among a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores at least pairs of a key value and a physical pointer value. The levels are sorted by time. New records are inserted in a created new highest (youngest) level. No edits are performed in-place. A data storage controller determines both a cost of searching a given table exceeds a threshold and an amount of memory used to flatten levels exceeds a threshold. In response, the controller incrementally flattens selected levels within the table based on key ranges. After flattening the records in the selected levels within the key range, the records may be removed from the selected levels. The process repeats with another different key range.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: May 30, 2023
    Assignee: PURE STORAGE, INC
    Inventors: Marco Sanvido, Richard Hankins, Mark McAuliffe, Neil Vachharajani