Abstract: A program generation apparatus according to one or more embodiments may extract, from a series of motions defined in a motion program, a motion to be corrected based on a difference in attribute between a first component indicated as a target of a component change and a second component to replace the first component, and generate a new motion program by correcting a command value of the extracted motion to compensate for the difference in the attribute.

Abstract: A vehicle control system for an agricultural vehicle comprising a processing circuit including a processor and memory, the memory having instructions stored thereon that, when executed by the processor, cause the processing circuit to receive position information associated with a position of at least one of a second agricultural vehicle or a vehicular implement, determine, based on the position information, an unloading point associated with a position of an unloading mechanism relative to a receiving container, store the determined position, operate at least one of the agricultural vehicle or the second agricultural vehicle to position the receiving container such that a subsequent unloading point is the same as the determined unloading point.

Abstract: This drive assistance device comprises an ACC unit, an abnormality detection unit for detecting an abnormality from a detector used to perform ACC, and a vehicle stop control unit for performing control to stop an ego vehicle when an abnormality is detected by the abnormality detection unit and an inter-vehicle distance to a preceding vehicle satisfies a certain condition.

Abstract: The present disclosure provides methods and systems for predicting a trip intent or destination while a user is traveling along a route. The method may comprise: (a) receiving a starting geographic location of the route and data about an identity of the user; (b) retrieving a trained classifier based at least in part on the data about the identity of the user; (c) using the trained classifier to predict the trip intent or destination based on the starting geographic location; and (d) while the user is traveling in a terrestrial vehicle along at least a portion of said route, presenting one or more transactional options to the user on an electronic device, wherein the one or more transactional options are identified based on the trip intent or destination predicted in (c).

Abstract: A control system (10) is suitable for use in one's own motor vehicle (12) and is set up and intended to determine the current driving situation of one's own motor vehicle (12) and other motor vehicles (28, 40) in the surroundings of one's own motor vehicle (12) by means of a surroundings sensor system and to assign the other motor vehicles (28, 40) to specific movement paths or not.

Abstract: As one aspect of the present disclosure, an electronic device is disclosed. The device may include: a volatile memory device; and a controller configured to be connected with a host processor and the volatile memory device, wherein the controller may be further configured to receive a swap-out request for first data in pages from the host processor, generate first compressed data by compressing the first data in response to the swap-out request, and store the first compressed data in the volatile memory device.

Abstract: A computing system includes a host processor, a plurality of accelerators that communicate with the host processor based on a communication interface, and a plurality of memory nodes that are connected with the plurality of accelerators through an interconnection network. A first data link is established between a first accelerator of the plurality of accelerators and a first memory node of the plurality of memory nodes, and a second data link is established between the first accelerator and a second memory node of the plurality of memory nodes.

Abstract: A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.

Abstract: A robotic cell calibration method comprising a robotic cell system having elements comprising: one or more cameras, one or more sensors, components, and a robotic arm. The method comprises localizing positions of the one or more cameras and components relative to a position of the robotic arm using a common coordinate frame, moving the robotic arm in a movement pattern, and using the cameras and sensors to determine robotic arm position at multiple times during the movement. The method includes identifying a discrepancy in robotic arm position between a predicted position and the determined position in real time, and computing, by an auto-calibrator, a compensation for the identified discrepancy, the auto-calibrator solving for the elements in the robotic cell system as a system. The method includes modifying actions of the robotic arm in real time during the movement based on the compensation.

Abstract: An example system includes: a production system skill library, with a plurality of skill blocks describing and encapsulating the realization part of the skills involved in the production process; a unified execution engine with a plurality of skill function blocks describing and encapsulating the interface part of the skills involved in the production process; to receive a production procedure programmed by a user based on the skill function blocks, and successively start each skill function block in the production procedure to call at least one corresponding skill block; and device agents for controlling devices in the production system. Each device agent is used to provide a unified interface to control the corresponding device to perform operations according to the operation instructions from the unified execution engine or the skill block.

Abstract: Systems and methods for generating ground-level terrain elevation models, preparing vector street data to assist in generating such models, and finding approximate elevation of any point using such terrain models are provided. Lidar data can be analyzed, and Lidar elevation values at roadway/street intersections can be used to determine a model of the ground-level elevation in an area or region. Outliers can be removed. The ground-level elevation at any point in the mapped area can be determined using elevation levels for nearby roadway intersections.

Abstract: Disclosed herein are system, method, and computer program product embodiments for adaptive caching for hybrid columnar databases with heterogeneous page sizes. An embodiment operates by scanning one or more pools comprising one or more pages of the same size in a buffer cache. The embodiment determines an increment of a reuse rate for the pools in the buffer cache within a time interval. The embodiment determines a cumulative reuse rate that is the sum of the increments of the reuse rate over several time intervals. The embodiment determines a gliding average reuse rate of the cumulative reuse rate over several time intervals. The embodiment compares the average reuse rates of the plurality of the pools to a threshold to dynamically determine whether a pool should reuse memory from the existing pages of the same pool or rebalance memory from one or more victim pools.

Abstract: Application placement for distributed applications, including: identifying, from amongst a plurality of disparate storage environments, a storage environment that contains data that can be utilized by a portion of a distributed application; and initiating execution of the portion of the distributed application in an execution environment that is communicatively coupled to the storage environment.

Abstract: A memory controller comprises a system bus interface that connects the MC to a system processor, a system memory interface that connects the MC to a system memory, a read buffer comprising a plurality of entries constituting storage areas, the entries comprising at least one read buffer entry (RBE) and at least one extended prefetch read buffer entry (EPRBE), read buffer logic, dynamic controls that are used by the read buffer logic, and an MC processor comprising at least one extended prefetch machine (EPM), each corresponding to one of the at least EPRBEs, where the MC processor is configured to allocate and deallocate EPRBEs and RBEs according to an allocation method using the dynamic controls.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The memory device is arranged in a plurality of logical planes and the controller is configured to write log data and user data to separate planes within the memory device, such that the log data and user data are isolated from each other on separate planes. The controller is configured to read log data from one plane and user data on another plane simultaneously, where the log data and the user data are isolated from each other on separate planes.

Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

Abstract: The embodiments herein describe a multi-tenant cache that implements fine-grained allocation of the entries within the cache. Each entry in the cache can be allocated to a particular tenant—i.e., fine-grained allocation—rather than having to assign all the entries in a way to a particular tenant. If the tenant does not currently need those entries (which can be tracked using counters), the entries can be invalidated (i.e., deallocated) and assigned to another tenant. Thus, fine-grained allocation provides a flexible allocation of entries in a hardware cache that permits an administrator to reserve any number of entries for a particular tenant, but also permit other tenants to use this bandwidth when the reserved entries are not currently needed by the tenant.

Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in memory. An embodiment includes a controller, and a memory having a plurality of physical units of memory cells. Each of the physical units has a different sequential physical address associated therewith, a first number of the physical units have data stored therein, a second number of the physical units do not have data stored therein, and the physical address associated with each respective one of the second number of physical units is a different consecutive physical address in the sequence. The controller can relocate the data stored in the physical unit of the first number of physical units, whose physical address in the sequence is immediately before the first of the consecutive physical addresses associated with the second number of physical units, to the last of the consecutive physical addresses associated with the second number of physical units.

Abstract: A method for managing a memory buffer, a memory control circuit unit, and a memory storage apparatus are provided. The method includes the following steps. Multiple consecutive first commands are received from a host system. A command ratio of read command among the first commands is calculated. The memory storage apparatus is being configured in a first mode or a second mode according to the command ratio and a ratio threshold. A first buffer is configured in a buffer memory to temporarily store a logical-to-physical address mapping table in response to the memory storage device being configured in the first mode, in which the first buffer has a first capacity. A second buffer is configured in the buffer memory in response to the memory storage device being configured in the second mode, in which the second buffer has a second capacity, which is greater than the first capacity.

Abstract: A device is connected via a coherence interconnect to a CPU with a cache. The device monitors cache coherence events via the coherence interconnect, where the cache coherence events relate to the cache of the CPU. The device also includes a buffer that can contain representations, such as addresses, of cache lines. If a coherence event occurs on the coherence interconnect indicating that a cache line in the CPU's cache is dirty, then the device is configured to add an entry to the buffer to record the dirty cache line.