Patents Examined by Ramon A Mercado
  • Patent number: 10740028
    Abstract: An LRU buffer configuration for performing parallel IO operations is disclosed. In one example, the LRU buffer configuration is a doubly linked list of segments. Each segment is also a doubly linked list of buffers. The LRU buffer configuration includes a head portion and a tail portion, each including several slots (pointers to segments) respectively accessible in parallel by a number of CPUs in a multicore platform. Thus, for example, a free buffer may be obtained for a calling application on a given CPU by selecting a head slot corresponding to the given CPU, identifying the segment pointed to by the selected head slot, locking that segment, and removing the buffer from the list of buffers in that segment. Buffers may similarly be returned according to slots and corresponding segments and buffers at the tail portion.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 11, 2020
    Assignee: DataCore Software Corporation
    Inventors: Ziya Aral, Nicholas C. Connolly, Robert Bassett, Roni J. Putra
  • Patent number: 10740010
    Abstract: A memory module includes a first type memory, a second type memory, a serial presence detect device and a controller. The serial presence detect device is configured to transfer capacity information of the second type memory to an external host device, during an initialization operation. The controller is configured to transfer a training command for the second type memory received from the external host device to the first type memory, during a training operation, which follows in time the initialization operation.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Joon Kim, Dae-Jeong Kim, Wonjae Shin, Yongjun Yu, Insu Choi
  • Patent number: 10740017
    Abstract: Aspects of the present disclosure relate to protecting the contents of memory in an electronic device, and in particular to systems and methods for transferring data between memories of an electronic device in the presence of strong magnetic fields. In one embodiment, a method of protecting data in a memory in an electronic device includes storing data in a first memory in the electronic device; determining, via a magnetic sensor, a strength of an ambient magnetic field; comparing the strength of the ambient magnetic field to a threshold; transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: August 11, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Chando Park, Wei-Chuan Chen, Sungryul Kim, Adam Edward Newham, Seung Hyuk Kang, Rashid Ahmed Akbar Attar
  • Patent number: 10740004
    Abstract: A computer program product is provided for efficiently managing storage in a multi-tiered storage system. The computer program product comprises a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processor to cause the processor to receive a command from an application, where the command is directed to at least one object. The program instructions are further executable by the processor to cause the processor to determine storage for the at least one object in a multi-tiered storage system based on the command, and store the at least one object in accordance with the determined storage.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Robert B. Basham, Joseph W. Dain, Evangelos S. Eleftheriou, Dean Hildebrand, Stan Li, Edward H. W. Lin, Harold J. Roberson, II, Slavisa Sarafijanovic, Thomas D. Weigold
  • Patent number: 10740246
    Abstract: A system in which first header data, second header data, a first logical array and a second logical array are stored in volatile random access memory. Each array position of the first logical array represents an identifier of a database column value and stores an offset value associated with an array position of the second logical array, and each array position of the second logical array stores a row position of the database column value.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: August 11, 2020
    Assignee: SAP SE
    Inventors: Carsten Thiel, Guenter Radestock
  • Patent number: 10740190
    Abstract: Technologies are described herein for providing secure data protection and recovery. A virtual data center can be created on backup servers to manage data backup for a specific client. Backups can be performed by a master server in the virtual data center initiating a secure network connection with a client computing device at a random or pseudo random time within a backup window specified by the client. A backup agent on the client computing device can execute a data mover program complied at the client's computing system but received from the master server to retrieve and save backup data at a random or pseudo random temporary location. The saved data can be transmitted and stored on data storage accessible only by a storage server. Backup data can be inspected in an isolated inspection server and be made retrievable through a secure data repository accessible by the client.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: August 11, 2020
    Assignee: IRON MOUNTAIN INCORPORATED
    Inventor: Eli Almog
  • Patent number: 10732885
    Abstract: An illustrative ISCSI server computing device provides user computing devices with “private writable snapshots” of a desired volume of data and/or further provides “private writable backup copies.” The ISCSI service is provided without invoking snapshot limits imposed by storage arrays and further without specialized backup software and pseudo-disk drivers installed on the user computing devices. A user can browse as well as edit personal versions of any number and/or versions of block-level backup copies—the “private writable backup copies.” Likewise, a user can browse and edit personal versions of any number of snapshots of one or more versions of one or more desired data volumes—the “private writable snapshots.” A user can have any number of co-existing private writable snapshots and private writable backup copies. Sparse files, extent-files, software snapshots, and/or media agents co-residing on the ISCSI server are used in the illustrative embodiments.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 4, 2020
    Assignee: Commvault Systems, Inc.
    Inventors: Sunil Kumar Gutta, Vijay H. Agrawal
  • Patent number: 10732868
    Abstract: Implementing a base set of data storage features for containers across multiple cloud computing environments. A container specification analyzer receives a container specification that identifies a container to be initiated, a volume to be mounted, and a native device driver to communicate with to facilitate mounting the volume. The container specification analyzer changes the container specification to generate an updated container specification that identifies a pass-through device driver to communicate with in lieu of the native device driver and identifies pass-through device driver data that identifies a data storage feature to be performed on data destined for the native device driver. The container specification analyzer returns the updated container specification for processing by a container initiator.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: August 4, 2020
    Assignee: Red Hat, Inc.
    Inventors: Huamin Chen, Bradley D. Childs
  • Patent number: 10725698
    Abstract: Provided is a controller which issues a first write command for writing all data of a burst access operation on a memory and a second write command for writing data of a burst access operation on a memory per byte. The controller includes a holding unit configured to hold a plurality of commands requesting access to the memory and a selection unit configured to select, in a case where the holding unit holds the second write command and a command that causes a first time penalty longer than a second time penalty needed between the first write command that is issued first and the second write command that is issued next, the second write command prior to the command.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: July 28, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Wataru Ochiai
  • Patent number: 10725914
    Abstract: An infrequently used method is selected for eviction from a code cache repository by accessing a memory management data structure from an operating system, using the data structure to identify a first set of pages that are infrequently referenced relative to a second set of pages, determining whether or not a page of the first set of pages is part of a code cache repository and includes at least one method, in response to the page of the first set of pages being part of the code cache repository and including at least one method, flagging the at least one method as a candidate for eviction from the code cache repository, determining whether or not a code cache storage space limit has been reached for the code cache repository, and, in response to the storage space limit being reached, evicting the at least one flagged method from the code cache repository.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventor: Marius Pirvu
  • Patent number: 10719448
    Abstract: A cache is presented. The cache comprises a tag array configured to store one or more tag addresses, a data array configured to store data acquired from a dynamic random access memory device, and a cache controller. The cache controller is configured to: receive a cache access request; determine, based on an indication associated with the cache access request, a cache access policy; and perform an operation to the tag array and to the data array based on the determined cache access policy.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: July 21, 2020
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventor: Xiaowei Jiang
  • Patent number: 10691347
    Abstract: The present disclosure techniques for implementing an apparatus, which includes processing circuitry that performs an operation based a target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than the first cache line, and a memory array. The apparatus includes one or more memory controllers that, when the target data block results in a cache miss, determine a row address that identifies a memory cell row as storing the target data block, instruct the memory array to successively output multiple data blocks from the memory cell row to enable the memory-side cache to store each of the multiple of data blocks in the second cache line, and instruct the memory-side cache to output the target data block to a coherency bus to enable the processing circuitry to perform the operation based on the target data block.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Richard C. Murphy, Anton Korzh, Stephen S. Pawlowski
  • Patent number: 10671534
    Abstract: Disclosed are a method for controlling a device including at least one memory, and a smart TV. The method comprises the steps of: receiving, from a remote controller, a signal for executing at least one application; outputting video data and audio data of the executed application; temporarily storing the executed application in an internal memory; swapping, to an external memory, a page corresponding to a specific application of the at least one application stored in the internal memory; and displaying information on the application swapped to the external memory.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 2, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Gunho Lee, Baeguen Kang
  • Patent number: 10671312
    Abstract: A storage system including a random access memory, a hard disk, a non-volatile memory and a processing circuit is provided. The hard disk includes a media cache. When the processing circuit is to store data in the random access memory to the hard disk, the data in the random access memory are firstly stored to the non-volatile memory. Afterwards, the data in the non-volatile memory are directly written to a number of continuous sectors in the hard disk without being stored in the media cache of the hard disk.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 2, 2020
    Assignee: ACER INCORPORATED
    Inventors: Yi-Jhong Huang, Tz-Yu Fu
  • Patent number: 10664396
    Abstract: A method and apparatus for performing a data transfer, which include a selection a data transfer operation mode, based on telemetry data, from a first operation mode where a first type of data is transferred from a memory of a computing system to one or more shared storage devices, and a second operation mode where a second type of data is transferred from the memory to the one or more shared storage devices, the first type of data being associated with a first range of address space of the one or more shared storage devices, the second type of data being associated with a second range of address space of the one or more shared storage devices different from the first range of address space. Furthermore, a data transfer from the memory to the one or more shared storage devices in the selected data transfer operation mode may be included.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: May 26, 2020
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Kshitij Doshi, Sujoy Sen
  • Patent number: 10657049
    Abstract: A memory control device may include a buffer memory in which data is accessed by a unit of a slot; and a buffer interface suitable for controlling an access to the buffer memory. The buffer interface may include a mapping table suitable for storing the mapping between multiple virtual slot identification information (VBIDs) and multiple physical slot identification information (PBIDs); a buffer allocation unit suitable for determining a start VBID of the mapping table and the number of slots (NID) based on a size of data to write in the buffer memory, and allocating PBIDs of a free status to a buffer slot sequence in the mapping table, the buffer slot sequence including slots determined based on the start VBID and the NID; and a buffer access unit suitable for accessing data at positions of the PBIDs of the buffer memory based on the mapping table.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 19, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong-Sop Lee
  • Patent number: 10649911
    Abstract: Embodiment of this disclosure provide techniques to support full memory paging between different trust domains (TDs) in compute system without losing any of the security properties, such as tamper resistant/detection and confidentiality, on a per TD basis. In one embodiment, a processing device including a memory controller and a memory paging circuit operatively coupled to the memory controller is provided. The memory paging circuit is to evict a memory page associated with a trust domain (TD) executed by the processing device. A binding of the memory page to a first memory location of the TD is removed. A transportable page that includes encrypted contents of the memory page is created. Thereupon, the memory page is provided to a second memory location.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Hormuzd M. Khosravi, Baiju Patel, Ravi Sahita, Barry Huntley
  • Patent number: 10642499
    Abstract: Disclosed is a memory controller including a command decoder suitable for generating a data identifier of read data by decoding a read command, an update unit suitable for updating information of the read data in response to the data identifier of the read data, and a data output control unit suitable for storing data read from a memory device according to the read command, and selectively outputting the stored data as the read data based on the updated information.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 5, 2020
    Assignee: SK hynix Inc.
    Inventor: Young-Ook Song
  • Patent number: 10635332
    Abstract: Data storage federation equipment manages data storage arrays on behalf of host computers. In particular, the data storage federation equipment provides media type queries to the data storage arrays, each media type query requesting media type identification for a particular logical unit of storage (LUN) on a particular data storage array. The data storage federation equipment further receives, in response to the media type queries, media type responses from the data storage arrays, each media type response identifying media type for a particular LUN on a particular data storage array. The data storage federation equipment further performs, based on the media type responses, memory management operations that adjust operation of LUNs on the data storage arrays on behalf of the host computers. The memory management operations are performed while the data storage federation equipment remains interconnected between the host computers and the data storage arrays.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 28, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Bo Wu, Guangliang Lei, Cynthia Burns
  • Patent number: 10635323
    Abstract: Embodiments of the present disclosure provide methods, apparatuses and computer program products for managing a storage system. The storage system comprises a plurality of cache devices and a bottom storage device, and the plurality of cache devices comprise a first cache device group and a second cache device group. The method according to an aspect of the present disclosure comprises: receiving an input/output (I/O) request for the storage device; in response to determining that the I/O request triggers caching of target data, storing the target data from the storage device into the first cache device group if the I/O request is a read request; and storing the target data into the second cache device group if the I/O request is a write request.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: April 28, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Bob Biao Yan, Bernie Bo Hu, Jia Huang, Jessica Jing Ye, Vicent Qian Wu