Abstract: An inserted device for connecting auxiliary storage units (2) to a data-processing assembly, the units being connected on the one hand by a daisy-chain control cable A connecting the storage units (2) to one another and to the data-processing assembly, inter alia to at least one auxiliary storage unit controller (3), and on the other hand by high transmission-speed star cables B, characterized in that it comprises means for disconnecting and connecting each auxiliary storage unit (2) in the data-processing assembly without interfering with the operation of the other auxiliary storage units (2), inter alia those connected to the same controller (3).

Abstract: Data packet circulates in the order of program storing portion, data pair producing portion and operation processing portion, so that operation processing based on the data flow program stored in the program storing portion progresses. Priority information is applied in advance to the data flow program stored in the program storing portion. If hash collision occurs in the data pair producing portion, the data pair producing portion determines priority for data pair production processing in accordance with the priority information, so that data pair production processing is first formed with respect to the data packet having higher priority.

Abstract: A microprocessor includes an execution unit executing a program according to an instruction, an instruction prefetch circuit storing a plurality of instructions to be executed by the execution unit, a refresh control circuit controlling a refresh operation of a dynamic memory coupled to an external bus and a control unit. The control unit receives bus access request signals from the execution unit and from the instruction prefetch circuit, respectively, and a refresh request signal from the refresh control circuit and sends a refresh grant signal to the refresh control circuit in response to the refresh request signal when both the bus access request signals are absent. The refresh control circuit generates a first refresh request signal and a second refresh request signal.

Abstract: A system for interrupting loading of data into a high speed memory device from main storage when a processor requests cache access. A high speed cache is connected to main storage for storing at least a subset of the data residing therein, and the cache can be directly accessed by a processor. In a preferred embodiment, a buffering device is connected to main storage and to the cache for buffering data to be loaded therein. The data buffer is adapted to receive data from main storage continuously and is adapted to transfer the data to the cache continuously unless the cache is being accessed by the processor.

Abstract: A method and apparatus is described for establishing a global binary assertion in a multiprocessor environment. The local objects have a three-value status variable: -active, disquiet-, -passive, quiet-, and -passive, disquiet- being the three values. First all local objects are made active. During execution, locally the assertion may hold, and thereupon a transition from active to -passive, quiet- is signalled to a global synchronizer process. Thereafter, cross-requests from a non-local object may reactivate a quiet object to the state -passive, disquiet-. The synchronizer process counts the transitions from active to -passive, quiet- and thus can detect when all objects are quiet. The local operations may represent a garbage collection system, wherein originally root items are colored grey and all other items white. In a marking phase, all grey items are successively accessed.

Abstract: A technique for providing skew compensation particularly in association with a pipelined processor. The skew occurs between first and second clock signals. The skew compensation technique of the invention provides for the proper transfer of information between stages even though the clock signals may have a skew greater than the inter-stage delay. A holding or latching means is provided between stages so as to hold the previous stage data for clocking into the subsequent stage register.

Abstract: A central processing unit with partitionable program and data memory includes a CRT (10) which is interfaced with an embedded program/data memory (14). The embedded memory (14) is a random access memory which has a user-defined partition address that defines an address above which all addresses are associated with program memory and below which all addresses are associated with data memory. The partition address is stored in a memory control register (106) and can be loaded therein upon initialization of the CPU (10). When the program address or the data address exceeds the address in the embedded memory (14), the CPU (10) is allowed to access external program memory (24) and external data memory (26). This is controlled by an allocation/range control logic circuit (108).

Abstract: Apparatus for controlling the operational speed of a peripheral multispeed record/playback device so that the device and a connected computer can communicate at a compatible data rate. When a speed control operation is initiated, the device generates index pulses at a rapid rate. The computer generates a series of n test pulses in response to the generation of the first index pulse. The computer then times how long the n test pulses take to be generated. The peripheral device is then told to run at the data rate represented by how long it took to generate the n test pulses.

Abstract: A wafer-scale integrated circuit comprises a few hundred modules which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs XINN, XINE, XINS, XINW from neighbouring modules and outputs thereto XOUTN, XOUTE, XOUTS, XOUTW, only one of which is enabled to by one of four selection signals SELN, SELE, SELS, SELW acting both on transmit path logic and on receive path logic in a return path. A RAM unit can be enabled by WRITE to write a block of data sent to RID via the transmit path and can be enabled by READ to read a block of data to ROD for return along the return path. The provision of SELN, etc. READ and WRITE is effected by configuration logic which includes a shift register and is responsive to a command mode signal CMND, on a line which runs to all modules in parallel. If, when CMND is asserted the bit currently in the transmit path is logic (, the module is not addressed.

Abstract: In a multiprocessor system having a hierachal memory device employing a virtual memory system, serial communication means which makes it possible for memory management units, which are disposed for CPUs, respectively, to communicate with one another, so that any change of common memory management information can be exchanged directly between the memory management units. As a result, it is not necessary for each CPU to inform the memory management unit of any change of the memory management information by an operating system, so that the overhead of communication between CPUs can be reduced and memory management can be made correctly without applying any load to the operating system even when any change occurs in the memory management information.

Abstract: A computer system and method for operating a computer system capable of running in mutually incompatible real and protected addressing modes, in which programs written for one mode can be run in the other mode without modification. The operating system using BIOS assembles two different common data areas for the two modes, each inclusive of device block pointers, function transfer table pointers, data pointers, and function pointers. The common data area for the real mode is assembled first. To assemble the pointers for the protected mode common data area, the offset values from the real mode area are copied directly, and then selector values are inserted whose physical addresses correspond to the segments of the corresponding pointers in the real mode area. The selector values are derived from a segment descriptor table.

Abstract: An I/O control system includes an I/O control unit, a plurality of I/O devices, the start process prior to a data transfer process of the I/O device being off-line processed from the I/O control unit, and a data transfer path for data transferring to the I/O device, the data transfer being performed for one I/O device at a time. The I/O control unit controls an I/O device in such a way that the start process of the I/O device completes at the time when another I/O device under data transfer completes its data transfer, thus improving the utilization of a data transfer path.

Abstract: The present invention provides a memory organization scheme for a high-performance memory controller. The memory organization of the present invention combines page mode techniques and interleaving techniques to achieve high-performance.Sequential pages of memory are interleaved between memory banks so that memory accesses which are a page apart will be to two different memory banks. A page is preferably defined by a single row, with 2K columns per row defining the number of bits in a page. Accesses to bits in the same page as a previous access omit the row pre-charge cycle, thus speeding up the memory cycle. Accesses to a separate bank of memory chips from the previous access are likewise speeded up since there is no need to wait for the completion of the cycle in the previous bank before initiating the cycle in the separate bank.

Abstract: A microprocessor includes an execution unit executing a program according to an instruction, an instruction prefetch circuit storing a plurality of instructions to be executed by the execution unit, a refresh control circuit controlling a refresh operation of a dynamic memory coupled to an external bus and a control unit. The control unit receives bus access request signals from the execution unit and from the instruction prefetch circuit, respectively, and a refresh request signal from the refresh control circuit and sends a refresh grant signal to the refresh control circuit in response to the refresh request signal when both the bus access request signals are absent. Thus, the refresh operation can be performed without exerting a harmful influence on the operations of the execution unit and the instruction prefetch circuit. The refresh control circuit may generate a first refresh request signal and a second refresh request signal.

Abstract: A document processing system includes an input device for inputting into the system document information, including line pitch information relating to lines of the document information. The document information is divided into at least two regions. Also provided is a document memory for storing the document information. The system also includes a line pitch information memory for storing a plurality of line pitch information relating to the lines of the document information in each of the regions. Also included are first and second deriving devices. The first deriving device derives, in accordance with line pitch information relating to one of the regions, a position of the line to be printed subsequently in one of the regions. The second deriving device derives, in accordance with the line pitch information relating to the other one of the region, a position of the line to be printed subsequently in the other one of the regions.

Abstract: A word-processing system or memory typewriter has the usual keyboard, input display and printer, including a correction ribbon for removing erroneous characters from a document held in the printer; together with a spelling dictionary stored within the memory, an error indicator activated upon entry of an incorrect word, and correction information and controls also stored in memory for amending the incorrect word into a trial word which matches one stored in the above-mentioned dictionary. For greater efficiency and ease of use by the operator, if the trial word is satisfactory when displayed, pressing the usual return key on the keyboard signals the system to print that trial word in place of the incorrect word on a printed document, only the erroneous characters being replaced so as to minimize use of the correction ribbon and the print ribbon in unnecessary removal and replacement of valid characters in the incorrect word.

Abstract: A method and apparatus for controlling access to its general purpose registers (GPRs) by a high end machine configuration including a plurality of execution units within a single CPU. The invention allows up to "N" execution units to be concurrently executing up to "N" instructions using the GPR sequentially or different GPR's concurrently as either SINK or SOURCE while at the same time preserving the logical integrity of the data supplied to the execution units. The use of the invention allows a higher degree of parallelism in the execution of the instructions than would otherwise be possible if only sequential operations were performed.A series of special purpose tags are associated with each GPR and execution unit. These tags are used together with control circuitry both within the GPR's, within the individual execution units and within the instruction decode unit, which permit the multiple use of the registers to be accomplished while maintaining the requisite logical integrity.

Abstract: A computer system in which peripherals greater in number than the number of DMA channels provided in the system can all have DMA access. Some of the DMA channels are dedicated to certain ones of the peripherals, while others, termed "programmable" DMA channels, are shared by remaining ones of the peripherals. Each peripheral having DMA access has a channel priority value. When a peripheral wants DMA access, it transmits its channel priority value onto an arbitration bus. The winning channel priority value is then compared with prestored DMA channel assignment values. If the comparison is successful, the corresponding peripheral is given a DMA channel corresponding to the DMA Channel assignment value with which the comparison was successful.

Abstract: All but one of the microcomputers in a multi-computer system are equipped with a rapid-access read-write memory and a fixed content nonvolatile read-only memory. Each of these read-only memories, however, stores a multiplicity of varieties of one or more sets of data, so that, in the case of a computer system for a motor vehicle engine, the same system can be used in any of a large number of vehicle models. One of the microcomputers of the system has a programmable memory which is programmed at the time of installation to designate the portions of the fixed memories that are to be utilized. When the system is turned on, the programmed memory designation number is stored in the read-write memory of all of the computers of the system, with the result that the designated portion of each fixed read-only memory is always referred to in any computer of the system. It is not important that, when the system is turned off, the memory content of the read-write memories is lost.

Abstract: According to a multipoint link data-transmission control system, a master transmission device delivers message data via a bidirectional transmission path to a plurality of slave transmission devices, the data containing a control field for designating control data for setting or resetting a flag. The transmitting of data from the slave transmission device to the master transmission device is allowed when the flag is set, and is inhibited when the flat is reset. Where the transmitting of data from a faulty slave transmission device is to be inhibited, the master transmission device transmits the data to the faculty slave transmission device, by designating flag reset data to the control field of the message data. As a result, a transmission-enable signal, which is delivered in synchronization with a transmission-timing clock signal, is reset, thereby stopping the transmitting of data from the slave transmission device to the master transmission device.