Abstract: To speed up data transfer, one embodiment of the invention features a transmission gate arrangement which pre-charges and transfers data in internal and external buses with the same timing and which further initializes the internal bus and a device such as an ALU, every bus cycle. A second embodiment speeds the data transfer in the buses by providing two data transfer paths through the interconnected buses and reducing the combined resistances of the internal and external buses.

Abstract: Independently from a register for storing a base address and a word counter for counting a word length, an address generating unit comprises a group of registers for storing a plurality of relative addresses, thereby successively generating regularly skipped addresses.

Abstract: An adapter is connected between a peripheral controller and an intelligent peripheral device. The adapter allows the peripheral device to communicate with the controller. The adapter has control logic rather than a microprocessor for transmitting and receiving data. The control logic is comprised of combinatorial logic circuitry and a command register. The command register allows the controller to configure the cominatorial logic circuitry in order to control adapter operation.

Abstract: A stand-alone graphics workstation including a digital computer host and a graphics processing subsystem is disclosed. Address data relating to the graphics subsystem components is mapped into the host system virtual memory. The application processes residing in the host are thereby able to communicate directly with the graphics subsystem components, as, e.g. the structure memory, without the need of a direct memory access hardware arrangement or device drivers.

Abstract: A data processing system comprises a main memory for receiving an input access virtual address, data, and a write instruction, converting the access virtual address into a real address, storing the data at the real address in accordance with the write instruction, and generating a response upon writing of the data; an execution section for selectively and sequentially executing a series of microinstructions in accordance with an input wait signal, generating a write instruction and an access virtual address upon execution of a write microinstruction, and outputting the write instruction, the access virtual address, and the data to the main memory; and a controller for generating a wait signal in accordance with the access virtual address and the write instruction from the execution section, and the response from the main memory, and outputting the wait signal to the execution section.

Abstract: A data communications arrangement for a distributed processor control system having a number of stations which can send and receive control data, includes a communications processor at each station effective for controlling the flow of control data over a serial communications bus. The communications processor is coupled to a dual ported memory device along with a functional processor which is effective for carrying out the actual operations of the process. The communications control processor is further effective for assembling frames of control data according to a predetermined arrangement which gives a timing preference to a first category of data over a second category of data. The assembled frame of control data will then include all of the first category of data and, with time remaining from a timing goal, will include a portion of the second category of data.

Abstract: A microprocessor system having a functional redundancy monitor operation mode. This processor system includes two processors, one processor to receive external signals from a monitored processor, and compare the external signals with signals generated internally every bus cycle. The monitoring processor then produces a comparison resultant signal, indicating if a match occurs. The processor further includes a timer circuit for defining a period during which the comparison resultant signal is output. After that period, the comparison result signal is set to a logic level representative of a misoperation of the processor monitored.

Abstract: A bus interface interrupt arrangement is disclosed which provides separate interrupt controllers for each bus in a multibus computer system where the processor is connected to one of the busses. Interrupt requests decided on each of the busses other than a primary bus to which the processor is connected are input along with interrupts from circuits connected to the primary bus to the interrupt controller for the primary bus. The interrupt request decided by the interrupt controller for the primary bus is connected to an interrupt input of the processor. All interrupt controllers are connected to the primary bus and may be accessed by the processor. When an interrupt from one of the busses other than the primary bus is chosen by the processor, the processor must read the interrupt controllers to determine first what bus, and then identify the circuit that generated the interrupt that has been acknowledged.

Abstract: A system and method which assumes that the process being evaluated is written in a highly concurrent language or at least is capable of high degree of concurrent operations. The parameters employed in the simulated concurrent performance have a direct affect on performance time.

Abstract: An improved real-time debugger accommodates high level language computer programs containing dynamic local data and process context switches. Information thus acquired is used to deduce the stack frame pointer. Inputs and outputs of a target processor are tapped to capture key instructions, particularly indicating context switches. A local tag memory in the debugger stores images of stack frames during context switches.

Abstract: Disclosed is an electronic exchange with a hot standby memory copy system including main storage devices that are duplexed wherein to improve the processing capacity of a central processing unit and make the best use of the speed of a cache memory, in an information processing apparatus provided with central processing units, main storage devices and cache memories all of which are duplexed, first-in first-out memories that are duplexed and connected to the central processing units, a unit for simultaneously writing data, when the central processing unit writes the data into the cache memory, into the first-in first-out memory, and a unit for writing, independently of an operation of the central processing unit, the contents of a currently used one of the first-in first-out memories into a standby one of the main storage devices are provided.

Abstract: Improvements in workstations which utilizes virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes directed to the support of alias addresses, i.e., two or more virtual addresses which map to the same physical address in real memory Specifically, alias addresses are created so that their low order address bits are identical, modulo the size of the cache (as a minimum) for user programs which use alias addresses generated by the kernel, or wholely within the kernel. For alias addresses in the operating system, rather than user programs, which cannot be made to match in their low order address bits, their pages are assigned as "Don't Cache" pages in the memory management unit (MMU) employed by workstations which utilize virtual addressing.

Abstract: The invention comprises a combined hardware and software method and apparatus for determining the size of memory located on a memory card inserted in the slot of a memory backplane of a computer system. The method and apparatus also provides a means for selecting the memory card which contains a requested memory location. Each memory slot has associated therewith a multibit code which indicates the size of the memory installed in the associated slot. The code from each slot is hardwired to the system memory controller which, given the codes can, as part of its memory initialization route, scan these bits and decode them in order to determine the amount of memory installed in each slot of the memory backplane.Each slot is further provided with an X-bit starting address which uniquely defines the lowest address available from the board inserted in the associated slot. The starting address from each slot is compared with the leftmost X-bits of the currently requested memory address.

Abstract: A data processor in which return from subroutine execution is not dependent on the presence of a particular instruction at the end of the sequence of instructions comprising the subroutine. The disclosed embodiment comprises a micro-programmable processor designed for servicing a timer subsystem. The return from subroutine apparatus comprises a decrementor which may be enabled to decrement once for each instruction executed by the processor and a return address register. A jump to subroutine instruction loads a return address into the return address register, enables the decrementor and loads the program counter with the address of the first instruction of the subroutine. When the decremento reaches a count of zero, the return address is loaded into the program counter. Provision is also made for using the same hardward to execute a single instruction a predetermined number of times before proceeding to the next instruction.

Abstract: In a queque device comprising a first-in-first-out memory device which has first through N-th memory stages and which successively shifts memorized signal units towards the N-th memory stage through which each memorized signal unit is successively produced as a basic sequence of output digital signal units, a supplementary memory is connected to a predetermined one of the memory stages that is for producing an additional sequence of output digital signal units. Both the output digital signal units of the basic and the additional sequences can be simultaneously produced in parallel in the form of two words and are delivered to an instruction execution unit. Thus, two words of the output digital signal units are quickly sent to the instruction execution unit. When each output digital signal unit of the basic sequence is sent from the N-th memory stage, the additional sequence is derived from the (N-1)-th memory stage.

Abstract: In a virtual machine system (VMS) capable of concurrently running at least one operating system (OS) under one real computer system and a control program (VMCP) for controlling the VMS, the object is to reduce the overhead produced for simulating VM I/Os by direct I/O execution. A VM information area of a real sub-channel control block has a status field in which a flag indicating that the sub-channel is dedicated or not is contained. When the flag is "1", it means that the sub-channel is dedicated to the VM and the sub-channel scheduling by the VMCP is not necessary. As a real interruption priority order is dedicated to a VM, only I/O interruption requests of the VM are queued into the real interruption request queue of that dedicated priority order, and the mixing of VMs in that real interruption priority order is avoided.

Abstract: A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.

Abstract: An information transfer from a first memory area to a second memory area is performed via a subsidiary memory. The information is read out of the first memory area by an upper portion of a first address designating the first memory area and is written into the subsidiary memory by a lower portion of a second address designating the second memory area. Thereafter, the information written into the subsidiary memory is read out thereof by a lower portion of the first address and is written into the second memory area by an upper portion of the second address. Thus, the information of the first memory area is rotated and transferred to the second memory area without shifting.

Abstract: A single-chip microcomputer includes therein an electrically programmable read-only memory (EPROM) including a specific cell of the EPROM storing an item of information for discrimination of memory space. When a reset signal is applied for initializing the single-chip microcomputer, the specific cell of the EPROM is selected and read out, and further latched in a latch circuit. On the basis of the content of the latch circuit, the single-chip microcomputer discriminates and sets a boundary between an internal memory and an external memory during programmed operation.

Abstract: A program storing portion in a data flow type information processor has one input port and two output ports. The two output ports are coupled to a paired data detecting portion through two transmission paths. A program storing portion has a copy function of generating a copy data packet from an original data packet. The original data packet is outputted to the paired data detecting portion through one of the transmission paths from one of the output ports. The copy data packet is outputted to the paired data detecting portion through the other transmission path from the other output port.