Patents Examined by Reema Patel
  • Semiconductor wafer storage system and method of supplying fluid for semiconductor wafer storage
    Patent number: 10964570
    Abstract: A semiconductor wafer storage system includes a container that provides a space in which a semiconductor wafer is to be stored, a fluid supply that provides a fluid to the container, a connection part that receives the fluid from the fluid supply and transfers the fluid to the container, and a nozzle part that connects the connection part to the container. The container may include a coupling plate to which the nozzle part is coupled, and the nozzle part may include a first nozzle and a second nozzle.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangkyung Lee, Yong-Jun Ahn, Taijo Jeon, Kyubum Cho, Jongsam Kim, Gi-Nam Park, Chul-Jun Park, Junyong Lee
  • Through silicon via design for stacking integrated circuits
    Patent number: 10964692
    Abstract: A three-dimensional (3D) integrated circuit (IC) and associated forming method are provided. In some embodiments, a second IC die is bonded to a first IC die through a second bonding structure and a first bonding structure at a bonding interface. The bonding encloses a seal-ring structure in a peripheral region of the 3D IC in the first and second IC dies. The seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. The bonding forms a plurality of through silicon via (TSV) coupling structures at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure by electrically and correspondingly connects a first plurality of TSV wiring layers and inter-wire vias and a second plurality of TSV wiring layers and inter-wire vias.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan, Jen-Cheng Liu, Alexander Kalnitsky, Yi-Sheng Chen
  • Semiconductor device and semiconductor device manufacturing method
    Patent number: 10957630
    Abstract: A semiconductor device includes: a circuit unit including a semiconductor chip; a plurality of pin terminals formed in a rod shape extending in a same direction from the circuit unit and electrically connected to the circuit unit; a sealing resin portion sealing the circuit unit and first portions of the plurality of pin terminals positioned on a side of the circuit unit; and a plurality of covering resin portions integrally extending from an outer surface of the sealing resin portion from which second portions of the plurality of pin terminals protrude, the plurality of covering resin portions being formed in a cylindrical shape respectively covering base end portions of the second portions of the plurality of pin terminals, which are positioned on a side of the sealing resin portion.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: March 23, 2021
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Soichiro Umeda, Atsushi Kyutoku
  • Tuning capacitance to enhance FET stack voltage withstand
    Patent number: 10951210
    Abstract: An RF switch to controllably withstand an applied RF voltage VSW, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of VSW appearing across it may be controlled to approximately zero.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: March 16, 2021
    Assignee: pSemi Corporation
    Inventor: Robert Mark Englekirk
  • Display apparatus and method of manufacturing the same
    Patent number: 10950681
    Abstract: A display apparatus includes a base substrate including a display area in which an image is displayed and a peripheral area adjacent to the display area, a source/drain pattern on the base substrate, the source/drain pattern including a connecting electrode in a pad portion of the peripheral area and a electrode of a thin film transistor in the display area, a planarization insulation layer on the base substrate, the planarization insulation layer contacting a side surface of the connecting electrode and a side surface of the electrode of the thin film transistor, and exposing a top surface of the connecting electrode, a connecting member contacting the connecting electrode, and a driving member including a driving circuit, the driving member being connected to the connecting member.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong Hyun Son, Sung Hoon Moon, Sung Jun Kim, Kohei Ebisuno, Deok Hoi Kim, Sanghoon Oh
  • Manufacturing method of semiconductor chip, and kit
    Patent number: 10942455
    Abstract: The present invention provides a manufacturing method of a semiconductor chip, in which the manufacturing yield is excellent, and a kit. According to the present invention, a manufacturing method of a semiconductor chip includes Process 1 of forming an insulating layer on a base material, Process 2 of forming a patterned resist film on the insulating layer, Process 3 of forming the insulating layer having an opening portion by etching the insulating layer with the patterned resist film as a mask, Process 4 of removing the patterned resist film, Process 5 of filling the opening portion of the insulating layer with metal, and Process 6 of performing chemical-mechanical polishing on the insulating layer filled with metal.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 9, 2021
    Assignee: FUJIFILM Corporation
    Inventor: Tetsuya Kamimura
  • Synthesis and use of precursors for ALD of group VA element containing thin films
    Patent number: 10941487
    Abstract: Atomic layer deposition (ALD) processes for forming Group VA element containing thin films, such as Sb, Sb—Te, Ge—Sb and Ge—Sb—Te thin films are provided, along with related compositions and structures. Sb precursors of the formula Sb(SiR1R2R3)3 are preferably used, wherein R1, R2, and R3 are alkyl groups. As, Bi and P precursors are also described. Methods are also provided for synthesizing these Sb precursors. Methods are also provided for using the Sb thin films in phase change memory devices.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: March 9, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami Pore, Timo Hatanpää, Mikko Ritala, Markku Leskelä
  • Semiconductor layer, oscillation element, and semiconductor layer manufacturing method
    Patent number: 10930522
    Abstract: A semiconductor layer of the present invention is a semiconductor layer including: a pn junction at which an n-type semiconductor (Al2O3 (n-type)) and a p-type semiconductor (Al2O3 (p-type)) are joined, the n-type semiconductor (Al2O3 (n-type)) having a donor level that is formed by causing an aluminum oxide film (Al2O3) to excessively contain aluminum (Al), the p-type semiconductor (Al2O3 (p-type)) having an acceptor level that is formed by causing an aluminum oxide film (Al2O3) to excessively contain oxygen (O).
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: February 23, 2021
    Assignee: UACJ Corporation
    Inventor: Koichi Ashizawa
  • Electronic component and three-terminal capacitor
    Patent number: 10930584
    Abstract: In an electronic component, a first ground land and a first hot land are provided on a mounting surface of a first substrate. A semiconductor chip is mounted on a first surface and a first ground land and a first hot land are provided on a second surface of a second substrate, and the second surface faces the mounting surface of the first substrate. A three-terminal capacitor is between the first substrate and second substrates.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: February 23, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Terutoki Kasamatsu, Syuichi Nabekura
  • Display apparatus including a shielding conductive layer
    Patent number: 10923549
    Abstract: A display apparatus including a shielding conductive layer is disclosed. The display apparatus includes a substrate, a driving thin film transistor disposed on the substrate, wherein the driving thin film transistor includes a driving semiconductor layer and a driving gate electrode, a scan line overlapping the substrate and extending in a first direction, a data line extending in a second direction crossing the first direction, wherein the data line is insulated from the scan line by an insulating layer, a node connection line disposed on a same layer as the scan line, and a shielding conductive layer disposed between the data line and the node connection line, in which a first end of the node connection line is connected to the driving gate electrode via a first node contact hole.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Wonse Lee, Kyunghoon Kim
  • Method for manufacturing a photovoltaic device
    Patent number: 10923618
    Abstract: The present disclosure provides methodologies for manufacturing high efficiency silicon photovoltaic devices using hydrogen passivation to improve performance. The processing techniques disclosed use tailored thermal processes, sometimes coupled with exposure to radiation to enable the use of cheaper silicon material to manufacture high efficiency photovoltaic devices.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: February 16, 2021
    Assignee: NEWSOUTH INNOVATIONS PTY LIMITED
    Inventors: Brett Jason Hallam, Stuart Ross Wenham, Roland Einhaus
  • LED display module and method of making thereof
    Patent number: 10923024
    Abstract: An LED display module contains a PCB, one or more layers of molding compound disposed on the surface of the PCB, a network of conductive tracks disposed on a surface of the one or more layer of molding compound away from the PCB, a plurality of through-holes extending through the one or more layers of molding compound, and an array of LED chips disposed in the one or more layers of molding compound. Each of electrodes on the LED chip is connected to one of the conductive pads via a conductive path. The conductive path comprises a conductive material inside one of the plurality of the through-holes and a portion of the network of conductive tracks.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 16, 2021
    Assignee: SCT LTD.
    Inventors: Shihfeng Shao, Chang Hung Pan, Heng Liu, Eric Li
  • Hybrid bonding contact structure of three-dimensional memory device
    Patent number: 10923491
    Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, multiple through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack, an array interconnection layer in contact with the through array contacts, a peripheral circuit formed on a second substrate. and a peripheral interconnection layer on the peripheral circuit.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: February 16, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Simon Shi-Ning Yang, Feng Pan, Steve Weiyi Yang, Jun Chen, Guanping Wu, Wenguang Shi, Weihua Cheng
  • Interconnect structure and method of forming the same
    Patent number: 10923392
    Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 16, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Soo Doo Chae, Jeffrey Smith, Gerrit J. Leusink, Robert D. Clark, Kai-Hung Yu
  • Method for mask-free OLED deposition and manufacture
    Patent number: 10923689
    Abstract: A method for making an OLED lighting panel is disclosed. A patterned inorganic insulating layer is used to enclose an area over a first electrode layer leaving portions of the first electrode layer and substrate adjacent to the outside of the enclosure exposed. After uniform deposition of the organic layer(s), the organic layer(s) are selectively removed over the inorganic insulating layer and an adjacent portion of the substrate to form a sealing region. After uniform deposition of the second electrode, the enclosed area is encapsulated and any overlying layers over the first and second electrodes outside the enclosed area are removed resulting in an OLED within the enclosed area with electrode contact pads outside the enclosed area. The OLED can be manufactured at low cost with no or limited use of shadow masking and is suitable for roll-to-roll processes.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 16, 2021
    Assignee: OLEDWorks LLC
    Inventors: John Hamer, Jeffrey Spindler
  • Micrometer scale light emitting diode displays on patterned templates and substrates
    Patent number: 10923628
    Abstract: Techniques, devices, and systems are disclosed and include LEDs with a first flat region, at a first height, including a plurality of epitaxial layers such as a first n-layer, a first p-layer, and a first active layer. A second flat region at a second height and parallel to the first flat region includes at least a second n-layer. Sloped sidewalls connect the first flat region and the second flat region and include at least a third n-layer. The p-layer of the first flat region is thicker that at least a portion of the third region. A p-contact is formed on the first p-layer and an n-contact is formed on the second n-layer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 16, 2021
    Assignee: Lumileds LLC
    Inventors: Costas Dimitropoulos, Sungsoo Yi, John Edward Epler, Byung-Kwon Han
  • Additive to phosphoric acid etchant
    Patent number: 10913893
    Abstract: Embodiments of compositions of a wet etchant and additive thereto for selectively etching silicon nitride to silicon oxide are disclosed. In an example, a composition of an additive to a phosphoric acid etchant includes an inhibitor and a dispersant. The inhibitor is absorbable on a surface of silicon oxide and capable of inhibiting etching of the surface of silicon oxide by the phosphoric acid etchant. The dispersant is capable of reacting with a by-product of a reaction between the phosphoric acid etchant and at least one of silicon oxide and silicon nitride and reducing a viscosity of the phosphoric acid etchant.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: February 9, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Rong Xu, Wenbin Sun, Jie Su
  • Method of selectively depositing a capping layer structure on a semiconductor device structure
    Patent number: 10910262
    Abstract: A method of selectively depositing a capping layer structure on a semiconductor device structure is disclosure. The method may include; providing a partially fabricated semiconductor device structure comprising a surface including a metallic interconnect material, a metallic barrier material, and a dielectric material. The method may also include; selectively depositing a first metallic capping layer over the metallic barrier material and over the metallic interconnect material relative to the dielectric material; and selectively depositing a second metallic capping layer over the first metallic capping layer relative to the dielectric material. Semiconductor device structures including a capping layer structure are also disclosed.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: February 2, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Aurélie Kuroda, Akiko Kobayashi, Dai Ishikawa
  • Flexible array substrate, flexible display device and method of assembling the same
    Patent number: 10910410
    Abstract: A flexible array substrate has a main display area, and includes a flexible substrate and a plurality of signal connecting portions. The flexible substrate includes at least one bent portion extending from at least one side of the main display area. The plurality of signal connecting portions are disposed at a side of the at least one bent portion away from the main display area. A plurality of signal lines are disposed on a first surface of the flexible substrate in the main display area. The plurality of signal connecting portions are configured to electrically connect the plurality of signal lines to at least one driving circuit. The at least one bent portion is configured to bend toward a second surface of the flexible substrate opposite to the first surface.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: February 2, 2021
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO.. LTD
    Inventor: Xiaolong Zhu
  • Chamferless via structures
    Patent number: 10903118
    Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: January 26, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss, Douglas M. Trickett