Abstract: The present invention discloses a MEMS device and electronic apparatus. The MEMS device comprises: a micro-LED; and a movable member, wherein the micro-LED is mounted on the movable member and is configured for moving with the movable member. According to an embodiment of this invention, the signal detection of a MEMS device can be simplified and/or the contents of signals produced by the MEMS device can be enriched.

Abstract: In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer, depositing a second epitaxial layer on the first epitaxial layer, implanting the second epitaxial layer to form a p-field termination region, depositing a third epitaxial layer on the p-field termination layer and forming trenches in the third epitaxial layer. The trenches include a trench gate of the transistor and a termination trench.

Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.

Abstract: A method of forming a semiconductor structure is provided. The method includes etching a trench in a template layer over a substrate, forming a seed structure over a bottom surface of the trench, forming a dielectric cap over the seed structure, and growing a single crystal semiconductor structure within the trench using a vapor liquid solid epitaxy growth process. The single crystal semiconductor structure is grown from a liquid-solid interface between the seed structure and the bottom surface of the trench.

Abstract: The present disclosure discloses a method for preparing an isolation area of a gallium oxide device, the method comprising: depositing a mask layer on a gallium oxide material; removing a preset portion region of the mask layer; preparing an isolation area in a position, corresponding to the preset portion region, on the gallium oxide material by using a high-temperature oxidation technique, with the isolation area being located between active areas of the gallium oxide device; and removing the remaining mask layer on the gallium oxide material. In the disclosure, the isolation area is prepared by using the high-temperature oxidation technique, which prevents damage to the gallium oxide device during the preparation of the isolation area, thereby achieving isolation between the active areas of the gallium oxide device.

Abstract: A packaged electronic component comprising: an electronic component housed within a package comprising a front part of a package comprising an inner section with a front cavity therein opposite the electronic component defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads adapted to couple the package in a flip chip configuration to a circuit board.

Abstract: A process for producing a donor substrate for creating a three-dimensional integrated structure comprises the following steps: providing a semiconductor substrate comprising a surface layer, referred to as an active layer, and a layer comprising a plurality of cavities extending beneath the active layer, each cavity being separated from an adjacent cavity by a partition, forming an electronic device in a region of the active layer located plumb with a cavity, depositing a protective mask on the active layer so as to cover the electronic device while at the same time exposing a region of the active layer located plumb with each partition, and implanting atomic species through regions of the active layer exposed by the mask to form a weakened zone in each partition.

Abstract: A display device includes: a substrate including a display area for displaying an image and a peripheral area positioned adjacent to the display area; a plurality of normal pixels disposed within the display area on the substrate, where each normal pixel includes a first transmissive area and a pixel area disposed adjacent the first transmissive area; and a dummy pixel disposed within the display area on the substrate, adjacent to a curved section of the peripheral area, and disposed between the peripheral area and the plurality of pixels. The dummy pixel includes: a second transmissive area; and a wire area disposed adjacent the second transmissive area.

Abstract: A method for treating a wafer is provided with a portion of a semiconductor layer is selectively removed from the wafer so as to create an inactive region of the wafer surrounding a first active region of the wafer. The inactive region of the wafer has an exposed portion of an insulator layer, but none of the semiconductor layer. The first active region of the wafer includes a first portion of the semiconductor layer and a first portion of the insulator layer. At least one conductor is formed in contact with the first portion of the semiconductor layer, such that the conductor and the first portion of the semiconductor layer form a portion of an electrical circuit. The first active region of the wafer is selectively treated to remove a native oxide layer from the first portion of the semiconductor layer. A resulting wafer is also disclosed.

Abstract: The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.

Abstract: According to an embodiment of the disclosure, a method of fabricating a carrier for a wafer level package (WLP) by using a lead frame, wherein the lead frame is fabricated by forming a trench and a post by performing first half etching on an upper surface of a base substrate comprising a conductive material, filling the first-half-etched surface with resin of an insulating material, removing the resin exposed to outside of the trench so that an upper surface of the trench and an upper surface of the resin are at a same level, and performing second half etching on a lower surface of the base substrate, in which a memory chip is attached to the lower surface of the base substrate.

Abstract: Disclosed are phototransistors, and more specifically a detector that includes two or more phototransistors, conductively isolated from each other. Embodiments also relate to methods of making the detector.

Abstract: A semiconductor device includes a semiconductor part, a metal layer, first and second electrodes, and first and second control electrodes. The first and second electrodes are provided on a front surface of the semiconductor part and arranged along the front surface of the semiconductor part. The first control electrode is provided between the semiconductor part and the first electrode. The second control electrode is provided between the semiconductor part and the second electrode. The metal layer covers a back-surface of the semiconductor part. The metal layer includes a first layer and a second layer. The first layer of the metal layer is electrically connected to the semiconductor part. The second layer of the metal layer is provided on the first layer inside a periphery of the first layer. The second layer has a layer thickness thicker than a layer thickness of the first layer.

Abstract: The present disclosure relates to a method of fabricating a semiconductor structure, the method includes forming an opening and depositing a metal layer in the opening. The depositing includes performing one or more deposition cycles, wherein each deposition cycle includes flowing a first precursor into a deposition chamber and performing an ultraviolet (UV) radiation process on the first precursor. The method further includes performing a first purging process in the deposition chamber to remove at least a portion of the first precursor, flowing a second precursor into the deposition chamber, and purging the deposition chamber to remove at least a portion of the second precursor.

Abstract: A semiconductor structure and a method for forming same are provided, the forming method including: providing a base including a plurality of adjacent device unit regions, an initial device gate structure spanning a plurality of device unit regions being formed on the base; etching a portion of the initial device gate structure in thickness at a junction between the adjacent device unit regions to form a top opening; forming a spacer layer on a side wall of the top opening; etching a remainder of the initial device gate structure exposed from the spacer layer, and forming a bottom opening exposed from the base within the remainder of the initial device gate structure, the remainder of the initial device gate structure being used as a device gate structure; and forming an isolation structure within the top opening and the bottom opening. The spacer layer is configured to adjust a width of the bottom opening, so that the width of the bottom opening is less than a width of the top opening.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gallium arsenide substrate, a thiourea-based passivation layer in contact with at least a top surface of the gallium arsenide substrate, and a capping layer in contact with the thiourea-based passivation layer. The method includes passivating a gallium arsenide substrate utilizing thiourea to form a passivation layer in contact with at least a top surface of the gallium arsenide substrate. The method further includes forming a capping layer in contact with at least a top surface of the passivation layer, and annealing the capping layer and the passivation layer.

Abstract: Aspects are directed to a MEMS device configurable to receive signals from a first, a second, a third, and a fourth signal source operating at a first, a second, a third, and a fourth frequency, respectively. The MEMS device may be configured to combine the first signal with the second signal generating a first combined signal, and to combine the third signal with the fourth signal generating a second combined signal. The first combined signal may be coupled to the first terminal of the MEMS device while the second combined signal may be coupled to the second terminal of the MEMS device. The first common terminal may be configured to produce an output associated with the second and fourth frequencies. The MEMS device may be further configured to derive from the produced output a signal indicative of nonlinearities or of changes in capacitance related to the MEMS device.

Abstract: A method of healing defects generated in a semiconducting layer by implantation of species made in a substrate to form therein an embrittlement plane separating a solid part of the substrate from the semiconducting layer, the semiconducting layer having a front face through which the implanted species pass. The method comprises local annealing of the substrate causing heating of the semiconducting layer, the intensity of which decreases from the front face towards the embrittlement plane. The local annealing may comprise a laser irradiation of a front surface of the substrate.

Abstract: A bonding apparatus and a bonding method are provided. The bonding apparatus bonds a semiconductor die to a substrate by thermocompression through an adhesive material. This bonding apparatus is provided with: a bonding tool which has a bonding surface that holds the semiconductor die through a first portion of a tape, and a pair of first tape constraining surfaces that are arranged so as to sandwich the bonding surface and constrain a second portion of the tape: tape constraining mechanisms which have a second tape constraining surface that presses the tape against the first tape constraining surfaces; and a control part which controls the movements of the bonding tool and the tape constraining mechanisms.

Abstract: An element chip manufacturing method including: a preparing step of preparing a substrate including a plurality of element regions and a dicing region defining the element regions, the substrate having a first surface and a second surface opposite the first surface; a laser scribing step of applying a laser beam to the dicing region from a side of the first surface, to form a groove corresponding to the dicing region and being shallower than a thickness of the substrate; a cleaning step of exposing the first surface of the substrate to a first plasma, to remove debris on the groove; and a dicing step of exposing the substrate at a bottom of the groove to a second plasma after the cleaning step, to dice the substrate into element chips including the element regions. The first plasma is generated from a process gas containing a carbon oxide gas.