Abstract: An external storage system is connected to a host system. A controller unit interposed between disk drives and the host system has a large capacity buffer memory with a battery providing non-volatile storage, a plurality of host interfaces and a plurality of drive interfaces. All the accesses made to the disk drives from the host system are realized via the buffer memory which allows a high-speed access. Read/write processing performed for the buffer memory by the host system is executed asynchronously with read/write processing performed between the buffer memory and the disk drives. The drive interface and the host interface area released during a period in which operation of the disk drive is waited for and recoupled upon data transfer.

Abstract: A system connects to an external contact pad that comprises a battery, a high-impedance load element powered by the battery and connected to pull a voltage potential of an external contact pad in a particular direction; a power supply connected to receive current from an AC line, the power supply carries a voltage; a switch connected to disconnect the power supply from the AC line; logic module connected to detect a voltage transition on the external contact pad caused when a user touches the external contact pad and to selectively operate the switch when the voltage transition is detected, the logic also connected to the battery and the power supply; and at least one microprocessor connected to be powered by the power supply.

Abstract: A communications protocol using group ordered message processing is disclosed. According to the protocol, a sending application groups messages together. The messages within the groups are then processed by a receiving application in the order received, but the groups themselves are processed in the order sent. More specifically, the invention pertains to a method for receiving messages at a processor node from another processor node via a plurality of communication paths. The method includes the steps of: receiving a message having a required number of messages value, comparing the required number of messages value with a number of processed messages, and determining whether the message is ready to be processed based on the result of the comparison. The invention can also be implemented as an apparatus. As an apparatus, the invention pertains to a processing node for a communication system which transmits messages between processing nodes interconnected by multiple communication paths.

Abstract: A method and corresponding apparatus for authenticating a client for a server when the client and server have different security mechanisms. An intermediary system known as an authentication gateway provides for authentication of the client using the client security mechanism, and impersonation of the client in a call to a server that the client wishes to access. The client logs in to the authentication gateway and provides a user name and password. Then the authentication gateway obtains and saves security credentials for the client, returning an access key to the client. When the client wishes to call the server, the client calls the authentication gateway acting as a proxy server, and passes the access key, which is then used to retrieve the security credentials and to impersonate the client in a call to the server. Any output arguments resulting from the call to the server are returned to the client through the authentication gateway.

Abstract: A system for operating and managing the network equipment is so adapted as to operate and manage a network in which plural computers and network devices are connected to each other. The system is provided with database storing data corresponding to the computers and the network devices and with means for preparing a network specification drawing which satisfies conditions required by the user from the data, for checking the physical data as to whether the network specification satisfies the physical data, for checking the logical data as to whether the network specification satisfies the logical data, and for displaying the network specification drawing in a two-dimensional or three-dimensional manner on the basis of the data stored in the database. The system for operating and managing the network equipment can reduce and simplify management business for network managers as well as management business for managing materials and products by managers managing the materials and products.

Abstract: A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, Y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.

Abstract: A method and apparatus for dynamically tuning a shared resource's bandwidth utilization, which enables system I/O software to control the length of burst accesses of a shared resource by peripheral components coupled to a peripheral component bus. The present mechanism enables the system I/O software to conduct empirical tests of bandwidth utilization by bus masters accessing the shared resource over the peripheral component bus. Based upon the empirical tests, the system I/O software can tune bandwidth utilization to attain a balance between peripheral component bus performance, and host bus performance.

Abstract: There is disclosed a shared multiprocessing system with several nodes, or processing units, interconnected together for communication purposes by a dual channeled crossbar switch. Several such multichannel crossbar switches can be linked together to form a large cohesive processing system where processing units from one node can access memory from another node on the same crossbar or from another node on a different crossbar. The interconnection between crossbars is accomplished by a circular ring. In operation, the system allows for long memory latencies while not increasing the length of short (local) memory latencies. This is accomplished by storing the bulk of long latency requests at the local processing unit and only sending the request when there is an actual availability of communication capacity to handle the long latency request.

Abstract: A novel high speed unidirectional bus system is provided for receiving a plurality of novel circuit card assemblies in receptacles on the bus. Adjacent receptacles are connected by lines on the bus which interconnect output pins to input pins. The circuit between output pins and input pins are formed by connecting the plugs on circuit card assemblies into the receptacles on said bus. The system comprises a plurality of function circuit card assemblies connected in a daisy chain when inserted into adjacent receptacles on said bus between a source circuit card assembly and a destination circuit card assembly and the address portion of the information supplied by the source circuit card assembly is programmed to identify the function circuit card assembly to first receive the source data whereby the unidirectional bus system may be operated in a time division random access mode at data rates in excess of the data rates of individual functional circuit card assemblies.

Abstract: A serial control apparatus is arranged so that an increased number of ICs mounted on a printed circuit card does not increase the number of signal lines for selecting the ICs. The serial control apparatus has a plurality of printed circuit cards each carrying a plurality of ICs and a CPU for controlling the plurality of ICs. Each card has a card match detecting means for identifying the card itself and generating a chip select signal to be sent commonly to all ICs on that card. Each of the ICs contains IC a match detector means for identifying the IC itself. The CPU generates serial identification signals including a card specification signal and an IC specification signal. Based on these signals and each of the match detectors, a particular IC on a particular card is selected.

Abstract: The system concept of the C3M2 System is to have the capability of providing a Processor for each major processing step of automated data processing, i.e. if you have four steps then you need a minimum of four but it could be 8 or 12 or 16 processors. The four major complementary functions encompass the four major functions of data processing (Input/Output, Data Computation, Storage and User I/F). The system shall be Multi-tasking for each step. Source headers, link lists and entity or object identifiers are the methods that shall be used for identity of the different classes, types and objects for the variety of data in the system. The source and data type are contained in the source header. The class and type identity are contained in the object identifiers. The multi-tasking would be by schedule (interleaved by priority). This was selected instead of cycle sharing for improved concurrency.

Abstract: A register-based computer architecture is particularly suited for using a common resource, such as a host processor or CPU, to respond to multiple devices such as co-processors, slave processors, or peripherals via service requests initiated by these devices. The invention's register acknowledgment and service prioritizing features are preferably added to, and integrated with, a prior-art, hardware-based interrupt acknowledgment mechanism, thus providing enhanced flexibility and performance. This architecture includes features for enhancing the support of a service-request based or queue-driven interface between the host processor and the supported devices, including a Service Request Status Register, a Service Request Configuration Register, and Service Request Acknowledge Register(s). From the point of view of the host processor, these registers are accessed as normal input/output read/write operations.

Abstract: A method for generating an optimized solution for assigning traffic loads to channels in SONET rings in cooperation with a computer having sufficient memory. The method utilizes a Mixed Integer Program (MIP) having corresponding variables necessary to model the cost of Terminal Multiplexers, Add/Drop Multiplexers and corresponding interface ports necessary to route the desired traffic loads. By routing traffic loads to reduce computation time and imposing mathematical bounds on the MIP variables, the number of possible MIP solutions is reduced. The Mixed integer Program is minimized in accordance with the traffic routing and imposed mathematical bounds such that an electrical signal is generated which corresponds to the optimized traffic load assignment information. The signal is converted to digital format whereupon it may be retrieved from computer memory and displayed to the user.

Abstract: A microprocessor having a register file inside is so combined with an external memory through a dedicated high-speed bus that the memory operates as a bank for said register file. This microprocessor further has means for controlling a data transfer with said memory or peripheral devices. When an address information to access said memory is input to this microprocessor in order to control a data transfer between said memory and a peripheral device, said control means finds if the accessed area in said memory is now in use as a bank for said register file, or not. When it is in use, said control means controls a data transfer between said peripheral device and said register file, instead of controlling the data transfer between said memory and said peripheral device. So, said peripheral device can always access the newest information in said memory.

Abstract: A common data link interface providing a framework for device drivers and data link providers. This interface allows multiple frameworks to coexist and share a single device driver. The common data link interface is framework independant and provides functions that are common to a plurality of frameworks. The common data link interface comprises three components, a network device driver, network demultiplexers, and network services. The network device driver provides a simple interface to network based devices that can be used by both the sockets IFNET and the streams DLPI data link layers. The network demultiplexor provides common data link receive functionality. Network services provides the remaining additional functionality required to bind the common data link interface together.

Abstract: A drive array controller is provided that serves as an interface between both stand-alone SCSI devices as well as SCSI devices that form a composite drive. Since an AHA emulation interface is incorporated on the drive array controller, the drive array controller is compatible with conventional AHA device drivers that drive stand-alone peripheral devices such as SCSI CD-ROM units and SCSI tape drives. The drive array controller includes a SCSI pass-through driver that extracts a SCSI command descriptor block from a command control block created by the AHA device driver. The drive array controller further provides a separate peripheral access channel to support high speed composite drive operations through a composite device driver. Since the AHA emulation interface and a composite drive interface are provided on a common peripheral board, only one EISA expansion slot is occupied.

Abstract: A method and system for providing services in an object oriented system. The method and system are in the form of an interface reference framework of objects which create services in response to requests. Clients request services which are created in response to the requests. In response to the request the framework first develops a description of the service. The description is in the form of a stack of descriptions of services. From the stack descriptions the actual services are created by maker objects.

Abstract: A multimedia network system (10) for connection to a computer (12) and a computer network (28). Asynchronous transmission mode cells on the network (28) are processed by a network interface board (22) with synchronous signals routed to an ISOBUS (26) and asynchronous signals routed through a packet memory (54) to the computer (12). Asynchronous signals are routed through the ISOBUS (26) to a video board (24) and converted for output to one or more audio/video output devices (36). Signals originating at one or more audio/video input devices (34) are processed through the video board (24) and the network interface board (22) to the network (28).

Abstract: A method and system are disclosed for efficiently reading and processing multiple data blocks stored in a removable data storage medium within a data storage system, wherein each data block includes a header portion containing selected parameters necessary to identify and process an associated data block, and a data portion. Each data block is accessed within the removable data storage medium utilizing track logic circuitry and then coupled to a data block buffer for temporary storage. A header processing logic circuit is interposed between the track logic circuitry and the data block buffer and is utilized to initiate processing of only the header portion of each data block prior to storage of the data block within the data block buffer. After completion of processing of the header portion of a data block and completion of storage of that data block within the data block buffer, the data block is efficiently processed utilizing selected parameters contained within the header portion.

Abstract: A "Personal Computer Memory Card International Association" (PCMCIA) peripheral, e.g., a modem, incorporates a shared memory interface to a personal computer. This shared memory interface provides the capability to easily program the PCMCIA peripheral either in the factory or in the field. In addition, the shared memory interface removes the requirement of having a resident "boot-up" code in the PCMCIA peripheral. Finally, the shared memory interface provides the capability to transfer user data from the personal computer, i.e., data terminal, to the PCMCIA modem at a higher data transfer rate than is currently available via the modem's universal asynchronous receive/transmit (UART) integrated circuit.