Abstract: In a system that executes the method according to the invention, each slot on the system bus is individually enabled at start-up and each address of an address range is read to determine whether an expansion board is installed in the slot and is responding to a read from that I/O address. If the data value returned by the I/O read is not equal to the undriven value of the data bus, then it is known that the expansion board is responding to that I/O address. Otherwise, a second read of the I/O address is performed, and the values of certain control lines on the system bus are latched to determine whether an expansion board is driving those lines in response to the I/O read. If so, again it is known that an expansion board is responding to a read from that I/O address. Otherwise, the system then performs a further special I/O read to determine the data bus response time.

Abstract: A store and forward switching system, typically for use as a facsimile system, has a plurality of communication control units for controlling transmission and reception of data through a plurality of respective communication lines, a multiplexer for transferring data to and from a selected one of the communication control units, a hard disk for storing data, a bulk processor for reading data from the hard disk and writing data in the hard disk, a main processor for controlling the multiplexer, the hard disk, and the bulk processor, and a system bus connected to the multiplexer, the bulk processor, and the main processor. The multiplexer and the bulk processor have first and second data transfer execution units, respectively, for transferring data between the multiplexer and the bulk processor through the data transfer bus without being handled by the main processor.

Abstract: Disclosed is a data processing system for presenting concurrent requests for access to peripheral devices up to the number of subchannels available for handling input/output operations. A computer system provides a plurality of subchannels and affiliated unit control blocks for input/output operations between main storage and the peripheral devices. The unit control blocks comprise two groups, including a first dedicated to the peripheral devices and a second group available for dynamic association with the peripheral devices on a demand basis. The unit control blocks are termed base unit control blocks and alias unit control blocks, respectively. Upon system initialization, alias unit control blocks for a given logical subsystem are linked in a free pool. To initiate an input/output operation a program executing on the CPU first queries a base unit control block for a target peripheral device to determine its availability.

Abstract: A system buffers first and second data buses having asynchronous, different frequency clocks. The system comprises a data buffer interposed between the first and second data buses to receive data from the first bus and supply data to the second bus. The also comprises a write address generator, coupled to the first bus to receive a data available signal and coupled to the data buffer, for generating an address in the data buffer to store the data received from the first bus. The data available signal increments the write address generator. A load record register is coupled to receive an indication that data is being written from the first data bus into the data buffer, and tracks locations in the data buffer which have received data from the first data bus. A read address generator is coupled to the data buffer, and generates an address of the next data, if any, that is stored in the data buffer to be read onto the second data bus.

Abstract: To enable wired-OR signal lines to be connected without interlock in a bus linkage unit for connecting the bus of a computer system with the bus of an expansion device or the bus of another computer system through a signal transfer path in which the signal mode is different from those of the buses. A shadow register 46 that acts on the level of wired-OR signal line 51 of the other bus is provided in each system. The level of wired-OR signal lines in each system is sent to the shadow register of the other system through a communication path. When the shadow register of the system is at a predetermined level, said system will not send the level of said wired-OR signal line to the other system. Interlock is eliminated by avoiding repetition of level transfer echoes between both systems in this way. Both systems are further provided with a shadow-shadow register 47 for forming a mirror image of the shadow register of the other system.

Abstract: An interbus interface module enables storage and transfer of commands, messages and data between parallel a dual system bus operating on a first protocol and a subrequestor bus operating on a second protocol. The interface module serves a first group of requestors, such as multiple processors and main memory, for handling data transfers to and from the subrequestor bus via said dual system buses while also handling data transfers to and from a second group of requestors connected to the subrequestor bus.

Abstract: DMA adapters which perform programmed data transfer operations in response to descriptors are programmed by information in the same descriptors (and adapter logic responsive to that information) to perform various ancillary control functions relative to addressable I/O devices that conventionally would be addressed and controlled directly by a host (higher level) system processor (e.g., the processor that prepares the descriptors). The ancillary control functions are variable programmably in number (e.g., in the disclosed embodiment, one descriptor can define 0, 1 or 2 discrete ancillary control operations) and effects produced by each operation are programmably variable (e.g., ancillary operation can be used by the adapter to alter states of addressed devices; for example, to prepare a device that has been transferring data in one direction, in a half-duplex mode, for transferring data in the opposite direction, or to switch to a full duplex mode, etc.).

Abstract: A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter.