Abstract: In the method of manufacturing a semiconductor device (1) with a semiconductor body (2), a doped zone (3) is formed in the semiconductor body (2). The semiconductor body (2) has a crystalline surface region (4), which crystalline surface region (4) is at least partly amorphized so as to form an amorphous surface layer (5). The amorphization is achieved by irradiating the surface (6) with a radiation pulse (7) which is absorbed by the crystalline surface region (4). The radiation pulse (7) has a wavelength which is chosen such that the radiation is absorbed by the crystalline surface region (4), and the energy flux of the radiation pulse (7) is chosen such that the crystalline surface layer (5) is melted. The method is useful for making ultra-shallow junctions.

Abstract: A process for hydrogen annealing silicon wafers that have been cut from an ingot and polished on both sides, thereby removing crystal originated pits (COPs) in their surface. The wafers are then stacked in a tower having at least support surfaces made from virgin polysilicon, that is, polysilicon form by chemical vapor deposition, preferably from monosilane. The tower may include four virgin polysilicon legs have support teeth slotted at inclined angles along the legs and fixed at their opposed ends to bases. The wafers so supported on the virgin polysilicon towers are annealed in a hydrogen ambient at 1250° C. for 12 hours.

Abstract: A method of dry etching a PCMO stack, includes preparing a substrate; depositing a barrier layer; depositing a bottom electrode; depositing a PCMO thin film; depositing a top electrode; depositing a hard mask layer; applying photoresist and patterning; etching the hard mask layer; dry etching the top electrode; dry etching the PCMO layer in a multi-step etching process; dry etching the bottom electrode; and completing the PCMO-based device.

Abstract: Methods of forming refractory metal suicide components are described. In accordance with one implementation, a refractory metal layer is formed over a substrate. A silicon-containing structure is formed over the refractory metal layer and a silicon diffusion restricting layer is formed over at least some of the silicon-containing structure. The substrate is subsequently annealed at a temperature which is sufficient to cause a reaction between at least some of the refractory metal layer and at least some of the silicon-containing structure to at least partially form a refractory metal silicide component. In accordance with one aspect of the invention, a silicon diffusion restricting layer is formed over or within the refractory metal layer in a step which is common with the forming of the silicon diffusion restricting layer over the silicon-containing structure.

Abstract: The invention encompasses methods of forming silicide interconnects over silicon comprising substrates. In one implementation, a first layer comprising a metal and a non-metal impurity is formed over a region of a silicon comprising substrate where a silicide interconnection is desired. An elemental metal comprising second layer is formed over the first layer. The substrate is annealed to cause a reaction between at least the elemental metal of the second layer and silicon of the substrate region to form a silicide of the elemental metal of the second layer. In another considered aspect, a method of forming a silicide interconnect over a silicon comprising substrate includes providing a buffering layer to silicon diffusion between a refractory metal comprising layer and a silicon containing region of a substrate.

Abstract: A vertical interconnect (15) in an electronic device (10) is manufactured non-photolithographically. This is done by modifying a surface (20,30) of either a metal layer (3) or an intermediate layer of an electrically insulating material (21), and subsequently depositing a composition with a first and a second polymer. Phase separation of the two polymers will lead to a first (6) and a second sub-layer (7), of which the first sub-layer (6) is removed. An upper layer (9) of electrically conducting material can be deposited then or after a further etching step. This results in the vertical interconnect (15).

Abstract: The present invention provides methods of manufacturing a MEMS assembly. In one embodiment, the method includes mounting a MEMS device, such as a MEMS mirror array, on an assembly substrate, where the MEMS device has a sacrificial layer over components formed therein. The method also includes coupling an assembly lid to the assembly substrate and over the MEMS device to create an interior of the MEMS assembly housing the MEMS device, whereby the coupling maintains an opening to the interior of the MEMS assembly. Furthermore, the method includes removing the sacrificial layer through the opening. A MEMS assembly constructed according to a process of the present invention is also disclosed.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip, a metal base, an insulative base and a conductive trace, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, the conductive trace includes a contact terminal that extends through the insulative base, and the pad is exposed through an opening that extends through the metal base and the insulative base and is spaced from the contact terminal, then forming a connection joint that contacts and electrically connects the conductive trace and the pad, and then removing a portion of the metal base that contacts the contact terminal. Preferably, the opening extends through an insulative adhesive that attaches the chip to the conductive trace.

Abstract: A method for the passivation of a semiconductor substrate, wherein a SiNx:H layer is deposited on the surface of the substrate (1) by means of a PECVD process comprising the following steps: the substrate (1) is placed in a processing chamber (5) which has specific internal processing chamber dimensions; the pressure in the processing chamber is maintained at a relatively low value; the substrate (1) is maintained at a specific treatment temperature; a plasma (P) is generated by at least one plasma cascade source (3) mounted on the processing chamber (5) at a specific distance (L) from the substrate surface; at least a part of the plasma (P) generated by each source (3) is brought into contact with the substrate surface; and flows of silane and ammonia are supplied to said part of the plasma (P).

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers (312, 314, 316, 318 and 320), using two etching sequences. A first etching sequence comprising: depositing a first etch mask layer (322), on the fifth (top) layer (320), developing a power line trench pattern (324) and a via pattern (326) in the first mask layer, simultaneously etching the power line trench pattern (324) and the via pattern (326) through the top three dielectric layers (316, 318, 320), and removing the first etch mask layer.

Abstract: A multi-component layer is deposited on a semiconductor substrate in a semiconductor process. The multi-component layer may be a dielectric layer formed from a gaseous titanium organometallic precursor, reactive silane-based gas and a gaseous oxidant. The multi-component layer may be deposited in a cold wall or hot wall chemical vapor deposition (CVD) reactor, and in the presence or absence of plasma. The multi-component layer may also be deposited using other processes, such as radiant energy or rapid thermal CVD.

Abstract: A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating fi

Abstract: A manufacturing method for a semiconductor integrated circuit device comprises forming, over a gate insulating film which has been formed over the main surface of a single crystal silicon substrate to have an effective film thickness less than 5 nm in terms of SiO2, a W film as a gate electrode material, and heat treating the silicon substrate in a water-vapor- and hydrogen-containing gas atmosphere having a water vapor/hydrogen partial pressure ratio set at a ratio permitting oxidation of silicon without substantial oxidation of the W film, whereby defects of the gate insulating film right under the W film are repaired. In this way, in a MISFET having a metal gate electrode formed over a ultra-thin gate insulating film having an effective film thickness less than 5 nm in terms of SiO2, defects of the gate insulating film can be repaired without oxidizing the metal gate electrode.

Abstract: Hydrogen gas sensors employ an epitaxial layer of the thermodynamically stable form of aluminum nitride (AlN) as the “insulator” in an MIS structure having a thin metal gate electrode suitable for catalytic dissociate of hydrogen, such as palladium, on a semiconductor substrate. The AlN is deposited by a low temperature technique known as Plasma Source Molecular Beam Epitaxy (PSMBE). When silicon (Si) is used the semiconducting substrate, the electrical behavior of the device is that of a normal nonlinear MIS capacitor. When a silicon carbide (SiC) is used, the electrical behavior of the device is that of a rectifying diode. Preferred structures are Pd/AlN/Si and Pd/AlN/SiC wherein the SiC is preferably 6H—SiC.

Abstract: A method of improving the tolerance of a back-end-of-the-line (BEOL) thin film resistor is provided. Specifically, the method of the present invention includes an anodization step which is capable of converting a portion of base resistor film into an anodized region. The anodized resistor thus formed has a sheet resistivity that is higher than that of the base resistor film.

Abstract: To provide a method for manufacturing a magnetic recording medium which creates anodically oxidized aluminum nanoholes so as to have a rectangular or elliptical sectional shape and gives shape anisotropy to a magnetic material filled in the nanoholes to thereby always fix a relative positional relation between magnetizations of the magnetic material and a magnetic head that detects the magnetizations. The method for manufacturing a magnetic recording medium includes: preparing a member having regularly arranged plural pits; subjecting the member to anodic oxidation treatment so that formation of holes is started with the pits as starting points, and a porous region, which has a first portion where the holes are formed without branching and a second portion where branched holes are formed, is formed; filling a magnetic material in the formed holes; and removing the non-branching portions of the holes.

Abstract: A method of nitriding an insulation film, includes the steps of forming nitrogen radicals by high-frequency plasma, and causing nitridation in a surface of an insulation film containing therein oxygen, by supplying the nitrogen radicals to the surface of the insulation film.

Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.

Abstract: Disclosed is a method of forming a barrier metal in the semiconductor device. The method comprises the steps of a) patterning a porous film on a base layer to form a via hole, b) depositing a CVD TiN film on the entire structure including the via hole, c) implementing a plasma treatment process using N2+H2, d) repeatedly implementing the steps (b) and (c) in order to bury only the pores formed on the surface of the porous film with CVD TiN, and e) forming a barrier metal on the entire structure including the via hole. Therefore, the present invention can prevent introduction of the conductive material into the base layer in a subsequent process.

Abstract: A system and method is disclosed for increasing the strength of a bond made by a small diameter wire in ball bonding. In one embodiment of the invention a structure for receiving a ball bond comprises substrate material that has portions that form a substrate cavity and a wire bond pad that covers and fills the substrate cavity. The wire bond pad also has portions that form a wire bond cavity for receiving the ball bond. The ball is wirebonded to the sides and bottom of the wire bond cavity. The sides of the wire bond cavity provide additional strength to the bond to resist shear and tensile forces that may act on the wire.