Abstract: A method of manufacturing a semiconductor device is disclosed. The manufacturing method comprises heating a reactor, setting a semiconductor wafer in the reactor, supplying a reactive gas into the reactor to form a film on the semiconductor wafer or on an inner surface of the reactor, and measuring a temperature change outside the reactor and a temperature change inside the reactor to determine a thickness of the film on the semiconductor wafer or on the inner surface of the reactor on the basis of a relationship between a ratio of the temperature changes and a thickness of the film.

Abstract: A magnetic memory array comprises a plurality of magnetic memory cells, a magnetic shielding disposed adjacent to at least one of the magnetic memory cells to reduce magnetic interference with respect to another of the magnetic memory cells, and an insulator disposed as to separate at least a portion of the magnetic shielding from the at least one magnetic memory cell. The magnetic shielding may be a magnetic shield layer, patterned magnetic shield materials, and/or magnetic particles embedded in the insulator.

Abstract: There are disclosed techniques for providing a simplified process sequence for fabricating a semiconductor device. The sequence starts with forming an amorphous film containing silicon. Then, an insulating film having openings is formed on the amorphous film. A catalytic element is introduced through the openings to effect crystallization. Thereafter, a window is formed in the insulating film, and P ions are implanted. This process step forms two kinds of regions simultaneously (i.e., gettering regions for gettering the catalytic element and regions that will become the lower electrode of each auxiliary capacitor later).

Abstract: A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate.

Abstract: The present invention provides a hydrogen barrier layer able to prevent diffusions of hydrogen into a capacitor and a method for fabricating a semiconductor device having the same. The inventive method includes the steps of: depositing a zirconium-titanium oxide layer containing zirconium, titanium and oxygen on a substrate; and performing a reforming process for densifying the zirconium-titanium oxide layer and for stuffing oxygen in a surface of the zirconium-titanium oxide layer.

Abstract: The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations. A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, strip, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer is 31 can be prevented.

Abstract: A method of manufacturing a light emitting device is provided which requires low cost, is easy, and has high throughput. The method of manufacturing a light emitting device is characterized in that: a solution containing a light emitting material is ejected to an anode or cathode under reduced pressure; a solvent in the solution is volatilized until the solution reaches the anode or cathode; and the remaining light emitting material is deposited on the anode or cathode to form a light emitting layer. A burning step for reduction in film thickness is not required after the solution application. Therefore, the manufacturing method, which requires low cost and is easy but which has high throughput, can be provided.

Abstract: The present invention provides a deposition method and deposition apparatus capable of forming a fluorine-containing silicon inorganic insulating film of stable film properties and a method of manufacturing a semiconductor device. Deposition apparatus 10 comprises parallel plate type electrodes 16, 22 arranged within reaction chamber 12, gas supply sources 20, 32, 34 for feeding process gas containing SiH4, SiF4 and oxygen source substance into reaction chamber 12, valves 36, 38, 40, gas mixing chamber 28 and power source 44 that supplies RF power for generating the plasma of the process gas. In this deposition apparatus 10, power source 44 is capable of supplying RF power of at least 1000 Watts to parallel plate type electrodes 16, 22. In this apparatus 10, fluorine-containing silicon oxide film is deposited on wafer 14 by generating the plasma of process gas containing SiH4, SiF4 and N2O.

Abstract: In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

Abstract: A method for forming a dielectric film in a PDP includes the steps of: reducing the ambient pressure of an insulating film including a dielectric material before the ambient temperature reaches the reaction temperature of the dielectric material; introducing heated gas to increase the ambient pressure up to the atmospheric pressure while maintaining the ambient temperature at the reaction temperature; and lowering the ambient temperature down to the solidifying temperature of the insulating film while maintaining the atmospheric ambient pressure.

Abstract: A method for fabricating a MTJ cell of a magnetic random access memory (MRAM) using a semiconductor film as a tunnel barrier layer is disclosed. The method comprises the steps of: forming a pinned ferromagnetic layer on a connection layer; forming a tunnel barrier layer using a semiconductor film on the pinned ferromagnetic layer; and forming a free ferromagnetic layer on the tunnel barrier layer.

Abstract: A system and method to form a stacked barrier layer for copper contacts formed on a substrate. The substrate is serially exposed to first and second reactive gases to form an adhesion layer. Then, the adhesion layer is serially exposed to third and fourth reactive gases to form a barrier layer adjacent to the adhesion layer. This is followed by deposition of a copper layer adjacent to the barrier layer.

Abstract: A lamp house storing a plurality of flash lamps and a chamber storing and holding a semiconductor wafer are fitted to each other in an openable/closable manner. The lamp house and the chamber are fixed to a closed state with male screws. In order to process a semiconductor wafer, a shutter plate is drawn out to open an irradiation window. In this state, the shutter plate shields a space located above the male screws so that the male screws cannot be detached for opening the lamp house and the chamber. In order to open the lamp house and the chamber, the shutter plate must be inserted for shielding the irradiation window while opening the space located above the male screws. Thus, a thermal processing apparatus capable of preventing the lamps from breaking during maintenance thereof is provided.

Abstract: A method of forming an image sensor array uses a transparent top conductive layer first as an etch mask in forming inter-pixel trenches and then as an etch stop in a planarization step, whereafter the top conductive layer is integral to operation of the completed image sensor array. During fabrication, a stack of layers is formed to collectively define a continuous photosensitive structure over an array area. The operationally dependent transparent top conductive layer is then used in the patterning of the photosensitive structure to form trenches between adjacent pixels. An insulating material is deposited within the trenches and the top conductive layer is then used as the etch stop in planarizing the insulating material. The method includes providing a connectivity layer that provides electrical continuity along the patterned top conductive layer.

Abstract: A metallic film (2) made of a metal on which an electroless plating film can be deposited is formed on part of the surface of a thermoelectric semiconductor (8) which is an object to be plated, made of a constituent material to which an electroless plating can not be directly applied, and subsequently, the thermoelectric semiconductor (8) is dipped in an electroless plating bath, whereupon a conductive film (3) having a uniform thickness, made up of an electroless plating film, is formed on the entire surface of the thermoelectric semiconductor (8) containing the surface of the metallic film (2).

Abstract: The present invention relates to a flip chip package comprising a chip assembly, a substrate, and an underfill material. The chip assembly has at least one chip. Each chips has a plurality of bond pads formed on a bottom portion of the chip. Each bond pad has a first solder bump formed on the bond pad. The chips are packaged by molding compound to form the chip assembly. The chip assembly has a bottom surface exposing a portion of the first solder bumps. The substrate has a plurality of support pads formed on a top surface of the substrate. Each support pad has a second solder bump formed on the support pad. The first solder bumps electrically connect to the second solder bumps to support the chip assembly by the substrate. The underfill material fills into a gap between the bottom surface of the chip assembly and the top surface of the substrate so as to form the flip chip package.

Abstract: A silicon nitride film and a silicon oxynitride film as an antireflection coating are successively formed on a silicon substrate. The silicon nitride film and the silicon oxynitride film are patterned. A reduction treatment for reducing the amount of oxygen atoms is performed on the silicon oxynitride film. The silicon oxynitride film after the reduction treatment and the silicon nitride film are used as a mask to etch the silicon substrate, thereby forming a trench in a main surface of the silicon substrate. This trench is filled with an insulating film.

Abstract: A plurality of liquids, the flow of each controlled by a volumetric flowrate controller, are mixed in a mixer to form a final precursor that is misted and then deposited on a substrate. A physical property of precursor liquid is adjusted by adjusting the volumetric flowrate controllers, so that when precursor is applied to substrate and treated, the resulting thin film of solid material has a smooth and planar surface. Typically the physical property is the viscosity of the precursor, which is selected to be relatively low, in the range of 1-2 centipoise.

Abstract: A process for the formation of structures in microelectronic devices such as integrated circuit devices. Vias, interconnect metallization and wiring lines are formed using single and dual damascene techniques wherein dielectric layers are treated with a wide electron beam exposure.

Abstract: In the manufacture of trench-gate power MOSFETs, trenched Schottky rectifiers and other devices including a Schottky barrier, a guard region (15s), trenched insulated electrode (11s) and the Schottky barrier (80) are self-aligned with respect to each other by providing spacers (52) to form a narrow window (52a) at a wider window (51a) in a mask pattern (51, 51s) that masks where the Schottky barrier (80) is to be formed. The trenched insulated electrode (11s) is formed by etching a trench (20) at the narrow window (52a) and by providing insulating material (17) and then electrode material (11s) in the trench. The guard region (15s) is provided by introducing dopant (61) via the wider window (51a). The mask pattern (51, 51s) masks the underlying body portion against this dopant introduction and is sufficiently wide (y8) to prevent the dopant (61) from extending laterally into the area where the Schottky barrier (80) is to be formed.