Patents Examined by Renee R. Berry
  • Patent number: 7105460
    Abstract: Methods are provided for depositing a dielectric material. The dielectric material may be used for an anti-reflective coating or as a hardmask. In one aspect, a method is provided for processing a substrate including introducing a processing gas comprising a silane-based compound and an organosilicon compound to the processing chamber and reacting the processing gas to deposit a nitrogen-free dielectric material on the substrate. The dielectric material comprises silicon and oxygen.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: September 12, 2006
    Assignee: Applied Materials
    Inventors: Bok Hoen Kim, Sudha Rathi, Sang H. Ahn, Christopher D. Bencher, Yuxiang May Wang, Hichem M'Saad, Mario D. Silvetti
  • Patent number: 7078341
    Abstract: A method for depositing metal layers on semiconductor substrates by a thermal chemical vapor deposition (TCVD) process. The TCVD process utilizes high flow rate of a dilute process gas containing a metal-carbonyl precursor to deposit a metal layer. In one embodiment of the invention, the metal-carbonyl precursor can be selected from at least one of W(CO)6, Ni(CO)4, Mo(CO)6, Co2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, and Ru3(CO)12. In another embodiment of the invention, a method is provided for depositing a W layer from a process gas comprising a W(CO)6 precursor at a substrate temperature of about 410° C. and a chamber pressure of about 200 mTorr.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: July 18, 2006
    Assignees: Tokyo Electron Limited, International Business Machines Corporation
    Inventors: Hideaki Yamasaki, Tsukasa Matsuda, Atsushi Gomi, Tatsuo Hatano, Masahito Sugiura, Yumiko Kawano, Gert J Leusink, Fenton R McFeely, Sandra G. Malhotra
  • Patent number: 7071104
    Abstract: A technique to form a structure with a rough topography in a planarized semiconductor process. The rough topography is formed by creating cored contacts. Subsequent process layers may be further stacked on top of the cored contacts in order to augment the nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: July 4, 2006
    Assignee: Altera Corporation
    Inventor: Raminda U. Madurawe
  • Patent number: 7067329
    Abstract: A ferroelectric memory device and a method of fabricating the same are provided. The device includes a substrate where a conductive region is formed and an interlayer insulating layer. The interlayer insulating layer is stacked on the substrate and has a contact hole exposing the conductive region. The contact hole is filled with a contact plug having a projection over the interlayer insulating layer. The projection of the contact plug is covered with a capacitor including a lower electrode, a ferroelectric layer pattern, and an upper electrode. A width of the projection is preferably greater than that of the contact hole and smaller than that of the lower electrode. The method includes forming lower and upper interlayer insulating layers on a substrate where a conductive region is formed. The lower and upper interlayer insulating layers have a contact hole exposing the conductive region.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: June 27, 2006
    Assignee: Samsung Electronics Co., LTD
    Inventor: Moon-Sook Lee
  • Patent number: 7067336
    Abstract: An electron-emitting device having favorable electron emitting characteristic stable for a long time, which is manufactured by a method comprising the steps of disposing an electrically conductive member having a second gap on a substrate, and applying a voltage to the electrically conductive member while irradiating at least the second gap with an electron beam from electron emitting means disposed apart from the electrically conductive member in an atmosphere comprising a carbon compound.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: June 27, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masafumi Kyogaku, Hironobu Mizuno, Takeo Tsukamoto, Hiroyuki Hashimoto, Koki Nukanobu
  • Patent number: 7052993
    Abstract: A thin film transistor and a method of manufacturing the same includes forming a copper alloy line on substrate, an oxidation film formed on the upper surface of the copper alloy line. The copper alloy line includes a concentration y of magnesium, and the copper alloy line has a thickness t. the concentration y of magnesium in copper alloy line is related to the thickness is as follows: y ? 94 t .
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: May 30, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Jae Gab Lee, Heung Lyul Cho
  • Patent number: 7052920
    Abstract: Methods and apparatus are disclosed for detecting a thickness of a surficial layer (e.g., metal or insulating layer) on a workpiece (e.g., semiconductor wafer) during a process for planarizing the layer, so as to stop the process when a suitable process endpoint is reached. Layer thickness is detected based on a spectral-characteristic signal of reflected or transmitted signal light, obtained by directing a probe light onto the surface of the workpiece. Example spectral characteristics are local maxima and minima of signal-light waveform, differences or quotients of the same, a dispersion of the signal-light waveform, a component of a Fourier transform of the signal waveform, a cross-correlation function of the signal waveform. Alternatively, the zeroth order of signal light is selected for measurement, or a spatial coherence length of the probe light is compared with the degree of fineness of the pattern on the surface illuminated with the probe light.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: May 30, 2006
    Assignee: Nikon Corporation
    Inventors: Yoshijiro Ushio, Takehiko Ueda
  • Patent number: 7053005
    Abstract: A method of forming a silicon oxide layer in a semiconductor manufacturing process includes forming a planar spin on glass (SOG) layer by coating an SOG composition onto a semiconductor substrate having a stepped portion formed thereon, pre-baking the substrate at a temperature of from about 100 to about 500° C. for about 1 to about 10 minutes, maintaining a loading temperature of a furnace into which the substrate will be loaded at about 500° C. or less, loading the substrate into the furnace, and main-baking the substrate at a temperature of from about 500 to about 1200° C. for about 10 to about 120 minutes to form a silicon oxide layer on the substrate. The SOG layer is transformed into the silicon oxide layer through an optimized process condition. Thus, the silicon oxide layer may have minimal defects and a good layer property.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: May 30, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Lee, Dong-Jun Lee, Jung-Sik Choi
  • Patent number: 7049247
    Abstract: A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: May 23, 2006
    Assignee: International Business Machines Corporation
    Inventors: Stephen M. Gates, Alfred Grill, David R. Medeiros, Deborah Neumayer, Son Van Nguyen, Vishnubhai V. Patel, Xinhui Wang
  • Patent number: 7041607
    Abstract: This invention describes a new method for forming and depositing thin films of crystalline dielectric materials. The present technique uses chemical synthesis to control the granularity and thickness of the dielectric films. This method has several key advantages over existing technologies, and facilitates the integration of crystalline dielectric materials into high-density memory devices.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: May 9, 2006
    Assignee: International Business Machines Corporation
    Inventors: Charles Black, Christopher Bruce Murray
  • Patent number: 7037785
    Abstract: Disclosed is a method of manufacturing the flash memory device.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: May 2, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cha Deok Dong, Ho Min Son
  • Patent number: 7030168
    Abstract: Supercritical fluid-assisted deposition of materials on substrates, such as semiconductor substrates for integrated circuit device manufacture. The deposition is effected using a supercritical fluid-based composition containing the precursor(s) of the material to be deposited on the substrate surface. Such approach permits use of precursors that otherwise would be wholly unsuitable for deposition applications, as lacking requisite volatility and transport characteristics for vapor phase deposition processes.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: April 18, 2006
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Chongying Xu, Thomas H. Baum
  • Patent number: 7018944
    Abstract: A method and apparatus that produces highly ordered, nanosized particle arrays on various substrates. These regular arrays may be used as masks to deposit and grow other nanoscale materials.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: March 28, 2006
    Assignee: NanoLab, Inc.
    Inventor: David L. Carnahan
  • Patent number: 7015052
    Abstract: A method for fabricating organic light-emitting diodes (OLEDs) and OLED displays using screen-printing, where a first electrode, at least one organic material, and a second electrode are formed on a substrate and at least one of the first and second electrodes and the at least one organic material is screen printed by positioning a screen with openings forming a pattern above a substrate and depositing a material onto the substrate through the openings. Exemplary embodiments include fabricating the electrodes and/or the at least one organic material as continuous layers or uniform, discrete blocks on the substrate and fabricating red, green, and blue OLEDs on the same substrate, which are then placed in OLED displays.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: March 21, 2006
    Assignee: The Arizona Board of Regents
    Inventors: Ghassan E. Jabbour, Dino P. Guzman, Nasser Peyghambarian
  • Patent number: 7008881
    Abstract: A silicon epitaxial layer is formed on the semiconductor underlayer of a target substrate (W) in the process chamber (2). This forming method includes a pressure reducing step of reducing the pressure inside the process chamber (2) accommodating the target substrate (W), a vapor phase growth step of introducing a film formation gas containing silane gas into the process chamber (2) to grow a silicon epitaxial layer on the semiconductor underlayer, and a hydrogen chloride treatment step and a hydrogen heat treatment step performed therebetween. The hydrogen chloride treatment step is arranged to introduce the first pre-treatment gas containing hydrogen chloride gas into the process chamber (2), thereby treating the atmosphere inside the process chamber (2). The hydrogen heat treatment step is arranged to introduce the second pre-treatment gas containing hydrogen gas into the process chamber (2), thereby treating the surface of the semiconductor underlayer.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: March 7, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Akitake Tamura, Satoshi Oka
  • Patent number: 7001844
    Abstract: Stress level of a nitride film is adjusted as a function of two or more of the following: identity of a starting material precursor used to make the nitride film; identity of a nitrogen-containing precursor with which is treated the starting material precursor; ratio of the starting material precursor to the nitrogen-containing precursor; a set of CVD conditions under which the film is grown; and/or a thickness to which the film is grown. A rapid thermal chemical vapor deposition (RTCVD) film produced by reacting a compound containing silicon, nitrogen and carbon (such as bis-tertiary butyl amino silane (BTBAS)) with NH3 can provide advantageous properties, such as high stress and excellent performance in an etch-stop application. An ammonia-treated BTBAS film is particularly excellent in providing a high-stress property, and further having maintainability of that high-stress property over repeated annealing.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: February 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Shreesh Narasimha, Victor Chan, Judson Holt, Satya N. Chakravarti
  • Patent number: 6995438
    Abstract: A semiconductor device includes a substrate and an insulating layer formed on the substrate. A conductive fin may be formed on the insulating layer. Fully silicided source and drain regions may be formed adjacent to the fin. A metal gate may be formed over a portion of the fin via a damascene process.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: February 7, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shibly S. Ahmed, Haihong Wang, Bin Yu
  • Patent number: 6989328
    Abstract: In copper plating using a damascene method, in order to prevent cost rise, dishing, erosion and the like due to the protrusion of plating on the dense wiring area to increase the time for CMP polishing, the copper plating is performed so that the current step of the copper plating has only one step for flowing current in the direction opposite to the direction of growing the plating as shown in FIG. 1. In this time, this opposite direction current step is performed under the condition of a current-time product within a range between 1.0 and 120 mA×sec/cm2.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: January 24, 2006
    Assignee: NEC Electronics Corporation
    Inventors: Koji Arita, Kaoru Mikagi, Ryohei Kitao
  • Patent number: 6984576
    Abstract: A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a metal base, an insulative base, a routing line and an interconnect, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, the routing line is disposed on a side of the insulative base that faces towards the chip, and the interconnect extends through a via in the insulative base and electrically connects the metal base and the routing line, forming an opening that extends through the insulative base and exposes the pad, forming a connection joint that electrically connects the routing line and the pad, and etching the metal base such that an unetched portion of the metal base forms a pillar that overlaps and is aligned with the via and contacts the interconnect, wherein a conductive trace includes the routing line, the interconnect and the pillar.
    Type: Grant
    Filed: February 1, 2003
    Date of Patent: January 10, 2006
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Cheng-Lien Chiang
  • Patent number: 6985384
    Abstract: A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Gregory Costrini, John Hummel, Kia-Seng Low, Igor Kasko, Frank Findeis, Wolfgang Raberg