Abstract: In a multicast capable IP network, each client terminal on a multimedia conference, for each media type it transmits, is assigned a multicast IP address and a port number (together known as a socket) on which to transmit packets, wherein each assigned multicast IP address is unique and different than the multicast IP address assigned to any other client for any media type. Each client terminal then selects, for each media type, which clients on the conference it wants to receive packets from. Only packets that are in fact requested by a client are routed over the multicast IP network to the requesting client. When a conference originator establishes the conference, a number of multicast IP addresses are allocated for later assignment to the clients during the conference. As each client joins the conference, it is assigned a multicast IP address from the allocated group for each media type it will transmit.

Abstract: A matrix switcher which is applied to a switcher system of a broadcasting station, connects a plurality of input lines and a plurality of output lines at any points, and outputs source video signals to be supplied from desired output lines, more particularly a matrix switcher capable of easily confirming inputs corresponding to the outputs. An operation panel 40 of the switcher system in which a plurality of inputs and a plurality of outputs are freely connected by switching is provided with cross point buttons 40A for selecting a plurality of inputs, source name display units 40N for displaying the source names being input, delegation buttons 45A selecting a plurality of outputs, and output source name display units 45N displaying the source names to be selected and output. Where the predetermined output is selected in the delegation button 45A, the source name displayed on the output source name display unit 45N is changed to a source name newly selected by the cross point button 40A.

Abstract: A method and apparatus is disclosed for translating data link layer and network layer frame headers at speeds approximating the reception rate of frames on respective communication links. High-speed header translation is achieved via the use of a dedicated microsequencer which identifies the receive frame encapsulation type and the transmit frame encapsulation type and based on such identification, selects a processing routine which is then executed to translate the frame header. The microsequencer is employed to control the movement of control information and frame header and payload information from an input FIFO, through the dedicated header processor, and to an output FIFO. The headers of the respective frames are translated within the dedicated header processor to facilitate header translation at high speeds. Via use of the presently disclosed header translation apparatus, layer 2 and layer 3 header translations, as well as other header translation functions may be rapidly performed.

Abstract: Logic circuits are employed in a telecommunications bridge/router device to examine a received frame to determine which VLAN, if any, the frame is associated with. The protocol type, receive port identification, and receive VLAN tag are employed to determine the transmit port identification and transmit VLAN tag. A predefined table indicates which ports within the bridge/router are associated with the VLAN. The frame is excluded from transmission through the ports that are not associated with members of the respective the VLAN.

Abstract: An InterPacket Gap (IPG) timer software object is given data packets, aka datagrams, from a system for transmission over a network medium. The IPG timer interfaces with a system-supplied timing mechanism for introducing an IPG between transmitted datagrams. Datagrams given to the IPG timer are enqueued for delivery, and, through the use of the system-supplied timer mechanism, delivered in the same order in which they were received to the network medium with a minimum time interval between the transmission of one datagram and the end of the transmission of the previous datagram.

Abstract: A method and apparatus are for receiving a portion of a message by a call receiver (2). A radio signal is intercepted (910) which is modulated with a hierarchical signalling protocol having variable bit rate protocol divisions (443). A particular variable bit rate protocol division (443) includes the portion of the paging message and a bit rate indicator (460). An optimum bit rate that is being used in the particular variable bit rate protocol division is determined (930) from the bit rate indicator (460). Words (450, 455) in the particular variable bit rate protocol division (443) are decoded (940) using the optimum bit rate. The portion of the paging message is obtained (950) from the words.

Abstract: A single chip integrated remote access processor circuit has a plurality of communication interface units, including a local area network (LAN) interface unit, a first multi-protocol serial wide area network (SWAN) interface unit, a telephony coder-decoder interface unit and a peripheral component interface (PCI) unit. A data routing control circuit is coupled to the plurality of communication interface units for controlling data transfer between the interface units.

Abstract: A circuit and method for framing an input data stream to a periodic signal. The circuit comprises a register circuit, a logic circuit and a multiplexor circuit. The register circuit may be configured to store information and to present a first and second output in response to (i) the input data stream and (ii) the periodic signal. The logic circuit may be configured to (i) detect a predetermined bit sequence and (ii) present a control signal in response to the information stored in the register circuit. The multiplexor circuit may be configured to present one or more multiplexed signals comprising the first and second outputs of the register circuit in response to the control signal.

Abstract: A port aggregation protocol (PAGP) dynamically aggregates redundant links between two neighboring devices in a computer network through the exchange of aggregation protocol data unit (AGPDU) frames between the two devices. Each AGPDU frame contains a unique identifier corresponding to the device sourcing the frame and a port number corresponding to the port through which the frame is forwarded. The exchange of AGPDU frames and the information contained therein allows the neighboring devices to identify those ports corresponding to the redundant links. Each device then dynamically aggregates its ports corresponding to the redundant links into a logical aggregation port (agport) which appears as a single, high-bandwidth port or interface to other processes executing on the device.

Abstract: A communication interface 122 for a network having a plurality of nodes 100-108 and a communication link 124,126 (120) connected between predetermined ones of the nodes 100-108 which propagates bus data, includes a first shared communication circuit 128, to be connected in series with the link 124,126, which receives the bus data and passes shared data along the link 124,126, a second shared communication circuit 136,142, connected to one port 129 of the circuit 128, which receives the bus data from the link 124,126 and passes the shared data, and which receives the shared data and couples the shared data onto the link 126, a first unshared communication circuit 144,148, connected to the port 129 of the circuit 128, which receives the bus data from the link 126 and passes the unshared data, and which receives the shared data and couples the unshared data onto the link 126, a second unshared communication circuit 130,134, connected to another port 127 of the circuit 128, which receives the bus data from the li

Abstract: A communications system is provided which supports asynchronous transfer mode (ATM) communications. An ATM multiplexer is located at a customer's premises and connected to customer premises voice and data equipment. A central office ATM multiplexer is connected to various different networks in the existing network infrastructure. The central office ATM multiplexer is preferably connected to networks such as a low-speed packet-switched network, a public circuit-switched network, a private line network, and a high-speed packet-switched network. The ATM multiplexer located at the customer premises preferably supports dynamic bandwidth allocation. Additional features provided by the communications system include the ability to provide different voice encoding schemes for different users based on calling party or called party information.

Abstract: A method for compensating for propagation time delays in a communication network includes connecting each of a plurality of subscribers to a ring feeder for a common transmission of digital source data and control data in a data stream synchronous with a clock signal. The source and control data are transmitted in a format prescribing a pulsed sequence of individual bit groups of identical length containing component bit groups each forming a data channel for source data or control data. At least two subscribers, which are connected at different locations to the ring feeder, receive source data that are transmitted by one of the subscribers on different data channels and are correlated with one another. Specific bit positions are reserved in each bit group for a numerical value relayed from subscriber to subscriber. The numerical value is always set by one of the subscribers to a fixed initial value and incremented by each following subscriber along the ring feeder.

Abstract: A dynamically reconfigurable, multi-mode, multi-channel communication bus. The bus may be dynamically reconfigured into a plurality fo segments, or slices, to provide a relatively wide unified bus, or smaller versions of the bus. This allows multiple bus masters to coexist at the same time that control the bus. The protocol is adaptive in that bus widths dynamically change to allow addition or removal of bus masters at any time. Bus acquisition delays caused by bus arbitration latency using a packetized protocol regime are drastically reduced or eliminated in some systems by using the present bus. The bus demonstrates relatively high efficiency.

Abstract: For a CDMA communication system using an interference canceller, a communication system which enables the interference canceller to easily confirm pulling-in of its own signal is disclosed. Input transmission signals are stored through a serial-parallel converter 101 in storage circuits 301 and 302, each of which holds one frame of transmission signals for I and Q axes. An area for holding one cycle of spreading codes for the I and Q axes output from a spreading code generator 105 is formed in the rearmost part of each of the transmission data strings of the storage circuits 301 and 302. One frame of transmission signals prepared by a pilot inserting device 102 and frame synchronizing signals are transferred to a transmitted circuit 103 in sequence. These signals are then transmitted as data for the I and Q axes by symbol rate clocks.

Abstract: A multicast engine of a shared-memory switching fabric circuit increases the replication rate of data elements destined for multicast connections within a network switch by manipulating address information relating to those elements. The multicast engine cooperates with other components of the switching fabric circuit to minimize the total buffer requirements of the switch by storing only a single copy of each multicast data element in a location of shared memory. Specifically, the engine has a pipelined architecture that provides a multicasting capability for the switching fabric circuit by replicating only an address pointer to that memory location for each destination of the multicast connection.

Abstract: An interfacing device having two operational amplifiers that have been manufactured on the same IC die have high-impedance input terminals connected directly to the two conductors of a local area network digital transmission line so as not to load or otherwise upset the impedance or other parameters of the transmission line. The output terminals of the operational amplifiers are connected to and match the input impedance of a digital transmission protocol analyzer. The gain of the operational amplifiers is arranged so as to replicate at the input of the analyzer the signals appearing on the local area network transmission line.