Abstract: A light receiving device comprises a substrate of a first type on a first electrode, a first region of the first type on the substrate, second regions of the first type arrayed on the first region, and third regions of a second type on the second regions. A first isolation portion is between the adjacent second regions and adjacent third regions. A second isolation portion comprising a metal is embedded the first isolation portions. A fourth region of the second type is on the first region and spaced from the second regions in a second direction with a pair of fifth regions thereon. An insulating film is on the fourth region and the pair of fifth regions. A second electrode is on the insulating film between the pair of fifth regions. The second electrode is comprised of the same metal as the second isolation portion.

Abstract: Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: providing a substrate in a reaction chamber; depositing a transition metal dichalcogenide thin film on the substrate using a sputtering process that uses a transition metal precursor and a chalcogen precursor and is performed at a first temperature; and injecting the chalcogen precursor in a gas state and heat-treating the transition metal dichalcogenide thin film at a second temperature that is higher than the first temperature. The substrate may include a sapphire substrate, a silicon oxide (SiO2) substrate, a nanocrystalline graphene substrate, or a molybdenum disulfide (MoS2) substrate.

Abstract: A semiconductor device has a substrate and graphene with semiconducting properties or diamond region formed on the substrate. The graphene with semiconducting properties or diamond region is formed on or within the substrate using liquid-phase-epitaxy growth of graphene enabled by a catalytic alloy of Ni and Cu. The substrate can be silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, or indium phosphide. A semiconductor component is formed over the graphene with semiconducting properties or diamond region and substrate. The semiconductor component can be a power MOSFET, IGBT, or CTIGBT with a gate structure formed over the substrate, source region adjacent to the gate structure, and drain region adjacent to the gate structure opposite the source region. The graphene with semiconducting properties or diamond region is formed under a gate of the MOSFET to reduce drain to source resistance, as well as providing radiation hardening for the device.

Abstract: A method of evaluating metal contamination by measuring the amount of metal contaminants to a silicon wafer in a rapid thermal processing apparatus includes steps of obtaining a Si single crystal grown by the Czochralski method at a pulling rate of 1.0 mm/min or lower, the crystal having oxygen concentration of 1.3×1018 atoms/cm3 or less, slicing silicon wafers from the Si single crystal except regions of 40 mm toward the central portion from the head of the single crystal and 40 mm toward the central portion from the tail, heat-treating the silicon wafer with a rapid thermal processing apparatus and transferring contaminants from members in a furnace of the rapid thermal processing apparatus to the silicon wafer, and measuring a lifetime of the silicon wafer to which contaminants are transferred.

Abstract: An IC includes a first and second active areas (AA) with a second conductivity type, a source and drain region, and an LDD extension to the source and drain in the first AA having a first conductivity type. A first bent-gate transistor includes a first gate electrode over the first AA extending over the corresponding LDD. The first gate electrode includes an angled portion that crosses the first AA at an angle of 45° to 80°. A second transistor includes a second gate electrode over the second AA extending over the corresponding LDD including a second gate electrode that can cross an edge of the second AA at an angle of about 90°. A first pocket distribution of the second conductivity type provides a pocket region under the first gate electrode. A threshold voltage of the first bent-gate transistor is ?30 mV lower as compared to the second transistor.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

Abstract: A cleaning method in an inspection apparatus that performs an electrical characteristic inspection on a device under test formed in an inspection object, includes: transferring, in a transfer process, a stage on which the inspection object is mounted to a position facing a probe card having probes, the probes being brought into contact with the device under test during the electrical characteristic inspection; subsequently, exhausting and depressurizing a space between the probe card and the stage facing the probe card in a peeling-off preparation process; introducing a gas into the space which has been depressurized and peeling off foreign substances adhering to a front surface of the stage and the probes in a foreign substance peeling-off process; and exhausting the space to discharge the foreign substances while continuously introducing the gas into the space in a foreign substance discharging process.

Abstract: Doped nitride-based semiconductor materials and methods of producing these materials are described herein.

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.

Abstract: Systems and methods are described for controlled crack propagation in a material using ultrasonic waves. A first stress in applied to the material such that the first stress is below a critical point of the material and is insufficient to initiate cracking of the material. A controlled ultrasound wave is then applied to the material causing the total stress applied at a crack tip in the material to exceed the critical point. In some implementations, the controlled cracking is used for wafering of a material.

Abstract: A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures.

Abstract: A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.

Abstract: Disclosed is a floating gate memristor device comprising: a substrate; a floating gate disposed on the substrate; an insulating layer covering the floating gate; a first electrode including a plurality of control terminals disposed on the insulating layer and spaced apart from each other, wherein the plurality of control terminals vertically overlap the floating gate; a second electrode spaced away from the first electrode, wherein a ground voltage is applied to the second electrode; and a third electrode disposed on the substrate and electrically connected to the floating gate.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

Abstract: According to various embodiments, a memory cell may include a substrate of a first conductivity type, the substrate having first and second regions of a second conductivity type spaced apart and defining a channel region therebetween. The memory cell may further include a word line arranged over a portion of the channel region nearer to the first region, an erase gate arranged over the second region, a floating gate arranged over another portion of the channel region nearer to the second region and between the word line and the erase gate, and a coupling gate arranged over a top end of the floating gate. The floating gate includes the top end, a bottom end, a first side extending from the top end to the bottom end and facing the erase gate, and a second side extending from the top end to the bottom end and facing the word line.

Abstract: The present invention provides various aspects for processing multiple types of substrates within cleanspace fabricators or for processing multiple or single types of substrates in multiple types of cleanspace environments particularly to form hardware based encryption devices and hardware based encryption equipped communication devices. In some embodiments, a collocated composite cleanspace fabricator may be capable of processing semiconductor devices into integrated circuits and then performing assembly operations to result in product in packaged form. Customized smart devices, smart phones and touchscreen devices may be fabricated in examples of a cleanspace fabricator. The assembly processing may include steps to form hardware based encryption.

Abstract: A method for fabricating a semiconductor device includes: forming a mold structure including a mold layer and a supporter layer over a semiconductor substrate; forming an opening penetrating the mold structure; forming a protective layer on a bottom surface and a sidewall of the opening; forming a lower electrode over the protective layer; selectively etching the supporter layer to form a supporter that supports the lower electrode; removing the mold layer to define a non-exposed portion and an exposed portion of an outer wall of the protective layer; and selectively trimming the exposed portion of the protective layer to form a protective layer pattern between the supporter and the lower electrode.

Abstract: A semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate electrode. The isolation layer is disposed on the substrate. The trench penetrates through the isolation layer and exposes a part of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate electrode is disposed on the semiconductor active structure. A manufacturing method of the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed penetrating through the isolation layer and exposing a part of the substrate. The semiconductor active structure is formed in the trench. The floating gate electrode is formed on the semiconductor active structure.

Abstract: A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the first and second areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in the first and second areas, forming a protective layer in the first and second areas and then removing the second conductive layer from the third area, then forming blocks of conductive material in the third area, then etching in the first and second areas to form select and HV gates, and replacing the blocks of conductive material with blocks of metal material.