Patents Examined by Richard Ellis
  • Patent number: 8250340
    Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: August 21, 2012
    Assignee: Panasonic Corporation
    Inventors: Shuichi Takayama, Nobuo Higaki
  • Patent number: 8200946
    Abstract: An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: June 12, 2012
    Assignee: International Business Machines Corporation
    Inventors: Christopher M. Abernathy, Kurt A. Feiste, Ronald P. Hall, Albert J. Van Norstrand, Jr.
  • Patent number: 8156312
    Abstract: An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configuration. The cell can be cascaded freely over a bus system, the EALU being decoupled from the bus system over input and output registers. The output registers are connected to the input of the EALU to permit serial operations. A bus control unit is responsible for the connection to the bus, which it connects according to the bus register. The unit is designed so that distribution of data to multiple receivers (broadcasting) is possible. A synchronization circuit controls the data exchange between multiple cells over the bus system. The EALU, the synchronization circuit, the bus control unit, and registers are designed so that a cell can be reconfigured on site independently of the cells surrounding it.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: April 10, 2012
    Inventors: Martin Vorbach, Robert Münch
  • Patent number: 8121828
    Abstract: A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: February 21, 2012
    Assignee: ATI Technologies ULC
    Inventors: John S. Yates, Jr., David L. Reese, Paul H. Hohensee, Stephen C. Purcell, Korbin S. Van Dyke
  • Patent number: 8074055
    Abstract: A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: December 6, 2011
    Assignee: ATI Technologies ULC
    Inventors: John S. Yates, Jr., David L. Reese, Korbin S. Van Dyke, Tiruvur R. Ramesh, Paul H. Hohensee
  • Patent number: 8065504
    Abstract: A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: November 22, 2011
    Assignee: ATI International SRL
    Inventors: John S. Yates, Jr., David L. Reese, Paul H. Hohensee, Korbin S. Van Dyke, Shalesh Thusoo, Tiruvur R. Ramesh
  • Patent number: 8055884
    Abstract: One embodiment of the present invention provides a system for augmenting a pipeline with a bubble-removal circuit. During operation, the system generates a bubble-removal circuit which determines a clock-enable signal based at least on whether an upstream register has valid data and whether the pipeline is stalled. Next, the system gates the clock signal using the clock-enable signal. The augmented pipeline can determine whether a first register contains invalid data, which is associated with a bubble. Next, the augmented pipeline determines whether a second register contains valid data, wherein the second register is adjacent to and upstream from the first register. If the first register contains invalid data and the second register contains valid data, the augmented pipeline replaces the invalid data of the first register with valid data based on the valid data in the second register without propagating the invalid data to a downstream register.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: November 8, 2011
    Assignee: Synopsys, Inc.
    Inventors: John D. Lofgren, Brett Kobernat
  • Patent number: 8019971
    Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: September 13, 2011
    Assignee: Panasonic Corporation
    Inventors: Shuichi Takayama, Nobuo Higaki
  • Patent number: 7991980
    Abstract: A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to receive executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: August 2, 2011
    Assignee: The Board of Governors for Higher Education, State of Rhode Island and Providence Plantations
    Inventors: Augustus K. Uht, David Morano, David Kaeli
  • Patent number: 7979684
    Abstract: A method of changing execution contexts is provided that includes receiving a context selection input. In a first clock phase, the method includes shifting data from a first latch element of a normal execution context to a second latch element of the normal execution context and shifting shadow data from a third latch element of a shadow execution context to a fourth latch element of the shadow execution context. In a second clock phase, the method includes shifting the shadow data of the fourth latch element of the shadow execution context into the first latch element of the normal execution context and shifting the data of the second latch element of the normal execution context into the third latch element of the shadow execution context. In a particular embodiment, the method may include receiving a test mode selection and shifting test data, such as scan test or automatic test pattern generated data, to a test output.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: July 12, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Jentsung Lin, Eai-Hsin Alfred Kuo, De Dzwo Hsu
  • Patent number: 7958337
    Abstract: An apparatus and method for executing instructions having a program order. The apparatus comprising a temporary buffer, tag assignment logic, a plurality of functional units, a plurality of data paths, a register array, a retirement control block, and a superscalar instruction retirement unit. The temporary buffer includes a plurality of temporary buffer locations to store result data for executed instructions, wherein the temporary buffer locations are arranged in a plurality of groups of temporary buffer locations. The tag assignment logic is configured to concurrently assign a tag to each instruction in a first set of instructions, wherein the tags are assigned such that the respective tag assigned to each of the instructions in the first set of instructions identifies a different one of the temporary buffer locations in a first one of the groups of temporary buffer locations.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: June 7, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Johannes Wang, Sanjiv Garg, Trevor Deosaran
  • Patent number: 7934078
    Abstract: An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: April 26, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Johannes Wang, Sanjiv Garg, Trevor Deosaran
  • Patent number: 7900026
    Abstract: A system for predicting multiple targets for a single branch includes: a branch target buffer that includes a previous next address for an instruction and that receives an indirect instruction address to provide a first branch target prediction; a first branch table for capturing local past target information of an indirect branch in an encoded form; a second branch table which is a correlation table for storing potential branch targets based on a local branch history and which provides a second branch target prediction when the first branch target prediction is not successful; an exclusion predictor for inhibiting updates of inefficient entries; and a multiplexer to select the predicted target as output.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: March 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Il Park, Mauricio J. Serrano, Jong-Deok Choi
  • Patent number: 7895419
    Abstract: A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Dan F. Greiner, Timothy J. Slegel, Joachim von Buttlar
  • Patent number: 7873817
    Abstract: A reduced instruction set computer (RISC) processor includes a processing core, which is arranged to process a software thread. A hardware-implemented scheduler is arranged to receive respective contexts of a plurality of software threads, to determine a schedule for processing of the software threads by the processing core, and to serve the contexts to the processing core in accordance with the schedule.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: January 18, 2011
    Inventors: Eli Aloni, Gilad Ayalon, Oren David
  • Patent number: 7849120
    Abstract: A microprocessor includes a random number generator circuit (RNG) within its instruction set architecture (ISA). An RNG buffer accumulates zero or more bytes of random data generated by the RNG. An RNG counter maintains a count of the accumulated random data bytes. An instruction translator translates instructions of the ISA. The ISA includes a distinct instruction that instructs the microprocessor to write the bytes from the buffer to a first user-visible register of the microprocessor and to load the count from the counter to a second user-visible register of the microprocessor. The count is unspecified by the instruction and may be between zero or more. In another embodiment, the instruction instructs the microprocessor to store a number of random data bytes specified from the buffer to a destination specified by the instruction, wherein the specified number may be greater than the maximum amount of bytes the buffer can hold.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: December 7, 2010
    Assignee: IP-First, LLC
    Inventors: G. Glenn Henry, Terry Parks
  • Patent number: 7844803
    Abstract: A data processing device has a configurable functional unit for executing an instruction according to a configurable function. The configurable functional unit has a plurality of independent configurable logic blocks for performing programmable logic operations to implement the configurable function. Configurable connection circuits are provided between the configurable logic blocks and both the inputs and the outputs of the configurable functional unit. This allows an optimalization of the distribution of logic functions over the configurable logic blocks.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: November 30, 2010
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Bernardo De Oliveira Kastrup Pereira, Jan Hoogerbrugge
  • Patent number: 7818358
    Abstract: A microprocessor includes a storage element that accumulates a variable number of bytes of random data. The microprocessor also includes a counter that maintains a count of the variable number of bytes accumulated in the storage element. The microprocessor also includes an instruction translator that translates an instruction specifying an address in a memory coupled to the microprocessor. The microprocessor also includes a store unit that stores to the memory at the address the variable number of bytes of random data from the storage element in response to the instruction translator translating the instruction. In one embodiment, the microprocessor atomically stores the count and the bytes accumulated in said buffer to the system memory. In one embodiment, an interrupt unit disables interrupts after the instruction translator translates the instruction and enables interrupts after execution of the instruction.
    Type: Grant
    Filed: December 25, 2006
    Date of Patent: October 19, 2010
    Assignee: IP-First, LLC
    Inventors: G. Glenn Henry, Terry Parks
  • Patent number: RE43145
    Abstract: A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: January 24, 2012
    Assignee: Panasonic Corporation
    Inventors: Toru Morikawa, Nobuo Higaki, Akira Miyoshi, Keizo Sumida
  • Patent number: RE43729
    Abstract: A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: October 9, 2012
    Assignee: Panasonic Corporation
    Inventors: Toru Morikawa, Nobuo Higaki, Akira Miyoshi, Keizo Sumida