Abstract: A computer simulator system allows the user to specify prototype reaction to events in a pictorial manner using a visual object environment. A spreadsheet like State Table and a visual object collection coincide on a common graphical display. The State Table is filled in by pointing to lists of events or actions associated with the different objects. The contents of these lists are dependent on the object class. Event or action descriptions are transported into the respective cells of the State Table in the form of descriptive strings of text. This text describes the event or action, and the event source, or action destination. Entries in the State Table define the operation of the simulation and are executed directly by an interpreter or are compiled to generate a program of instructions for performing the simulation.

Abstract: A microcomputer includes a CPU for processing data, a memory for storing a program for operating the CPU, an input circuit for detecting an input signal exceeding a threshold voltage that lies outside a range from zero volts to a power supply voltage and for supplying a detected input signal exceeding the threshold voltage to the CPU and an output circuit for outputting from the microcomputer a signal output by the CPU. The input circuit reduces power consumption and may include a differential circuit having a pair of transistors with different electrical characteristics, eliminating the need to establish a reference voltage with resistors or other components.

Abstract: Disclosed is an information processor comprising multiple instruction setup units which fetch and decode instructions as the first half of the procedure in instruction pipelines, each of the instruction setup units being in charge of processing instruction streams. The decoded results are scheduled in instruction schedule units and sent to each corresponding function unit to be executed.

Abstract: A multiprocessor system which includes a control processor and a high-level data-transfer processor. Both of these two processors are docked by a shared variable-duration clock. The duration of the clock is adjusted on the fly, to accommodate whichever of the two processors needs the longest cycle time on that particular cycle. Thus, the control processor 110 and the data transfer processor 120 are enabled to run synchronously, even though they are concurrently running separate streams of instructions.