Abstract: A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instructions and a load/store/operate organization. The hardware CISC instruction decoder is exposed for execution by user-state programs in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects. The CISC decoder is designed to decode a portion of an instruction set for the computer, and to deliver the decoded instructions to an instruction execution pipeline designed to execute the output of both the RISC instruction decoder and the CISC instruction decoder. A software emulator is programmed to implement a remainder of the instruction set.

Abstract: A data processing system with a microprocessor. The microprocessor has an instruction execution pipeline including fetch and decode stages and several functional execution units. Fetch packets contain a plurality of instruction words. Execute packets include a plurality of instruction words that can be executed in parallel by two or more execution units. An execution packet can span two or more fetch packets. A predetermined bit in each instruction marks whether the next instruction is executed in parallel with the current instruction. Instructions in an execute packet are dispatched to appropriate functional execution units based on instruction type. Upon a branch into an execute packet instructions at memory addresses before the branch location are not executed in parallel with instructions following the branch location.

Abstract: The present invention relates to a method and system for providing an N-way select instruction in a processor. Specifically, a method for providing an N-way select instruction includes decoding an instruction as an N-way select instruction. The method also includes selecting at least one pair of source operands from a plurality of instruction operands using information from a plurality of parallel control registers. The method, further includes selecting a final source operand from each of the selected at least one pair of source operands, and outputting each of the selected final source operands. In general, any N-way select instruction will have M=log2N stages of operation.

Abstract: A register window spill technique for an retirement window having an entry size less than a number of spill instructions used in a spill condition is provided. The technique uses modified spill instructions that allow the retirement window to retire a portion of the spill instructions without having to determine whether a remaining portion of the spill instructions will execute without exceptions.

Abstract: A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise at least one Micro-Engine (ME) arranged to establish connections and support data transfers, via a switched fabric, in response to work requests from a host system for data transfers; interface blocks arranged to interface the switched fabric and the host system, and send/receive work requests and/or data messages for data transfers, via the switched fabric, and configured to provide context information needed for said Micro-Engine (ME) to process work requests for data transfers, via the switched fabric, wherein the Micro-Engine (ME) is implemented with a pipelined instruction execution architecture to handle one or more ME instructions and/or one or more tasks in parallel in order to process data messages.

Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

Abstract: An apparatus for a processor includes a first scoreboard, a second scoreboard, and a control circuit coupled to the first scoreboard and the second scoreboard. The control circuit is configured to update the first scoreboard to indicate that a write is pending for a first destination register of a first instruction in response to issuing the first instruction into a first pipeline. The control circuit is configured to update the second scoreboard to indicate that the write is pending for the first destination register in response to the first instruction passing a first stage of the pipeline. Replay may be signaled for a given instruction at the first stage. In response to a replay of a second instruction, the control circuit is configured to copy a contents of the second scoreboard to the first scoreboard. In various embodiments, additional scoreboards may be used for detecting different types of dependencies.

Abstract: A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to recieve executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.

Abstract: An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results.

Abstract: A system for designing and implementing digital integrated circuits utilizing a set of synchronized sequencers that permit quick and efficient parallel processing of system level designs. The system and method converts digital schematics and hardware description language (HDL) based designs into a set of logic equations and single bit arithmetic-logic operations executed by a set of parallel operating sequencers. The system includes software for converting netlists and HDL designs into Boolean logic equations, and a compiler for distributing these logic equations between multiple sequencers. Each sequencer is comprised of a logic processor and the associated program memory for storing the executable code of the assigned Boolean logic equations and data memory for storing the results of processing of logic equations. To synchronize execution of logic equations by multiple sequencers, all program memories are addressed by one common address register.

Abstract: A processor is described which executes an instruction defined to swap the contents of at least one special purpose register (e.g. an MSR or a segment register) and another register. In some implementations, both of the registers are special purpose registers (e.g. a segment register and an MSR). The instruction may be used to provide a pointer to an operating system data structure in a register useable for address generation, and to preserve the content of that register in the other register involved in the swap. For example, in the segment register/MSR embodiment, the MSR may store the pointer and the segment register base address may be used in address generation operations.

Abstract: A method includes maintaining a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status for an associated thread of multiple threads being executed within a multithreaded processor. Status for a first thread is detected, responsive to which a functional unit within the multithreaded processor is configured in accordance with the multi-bit output of the state machine.

Abstract: A pipeline processor having an exception program counter chain generates a return address in the exception program counter chain for an executing instruction. The return address is the point at which instruction execution should resume after an exception handler routine runs if the executing instruction incurs an exception. The return address is stored into a profiling register if and when the corresponding instruction completes execution. The profiling register is periodically sampled and a statistical profile is built of instructions executed in the processor by using the return addresses sampled. A sampled return address is identified as a branch delay instruction and included in the statistical profile if the sampled return address is that of a branch instruction which immediately precedes a branch delay instruction.

Abstract: A method for determining a process to use for converting instructions in a target instruction set to instructions in a host instructions set including the steps of executing code morphing software including an interpreter and a translator to generate host instructions from target instructions, detecting at intervals whether the interpreter or the translator is executing, increasing a count if the interpreter is executing and decreasing the count if the translator is executing, and changing from interpreting to translating a sequence of target instructions when the count reaches a selected maximum.

Abstract: A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address of a first set of bytes including a branch instruction and a second address of a second set of bytes contiguous to the first set. The least significant bits of the branch PC (those bits not included in the most significant bits of the addresses received by the circuit) are used to generate the least significant bits of the link/sequential address and to select one of the first address and the second address to supply the most significant bits.

Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

Abstract: According to one embodiment, a method features operations for executing instructions in an instruction window. The first and second instructions are examined to determine their sources and destinations. The written on bit of the first instruction is set to a “written on” state if the destinations of the first and second instructions are the same while a used bit of the first instruction is set to a “used” state if the source of the second instruction is the destination of the first instruction. Thereafter, a priority of the first instruction can be determined from the written on and used bits.

Abstract: To provide a method of implementing cache logic technique in which total data processing time can be reduced, input data divided into block is sequentially processed in units of block in plural circuits using a programmable logic device provided with a circuit information input controller, a programmable logic circuit sector and a data cache. The plural circuits are sequentially reconfigured in the programmable logic device and execute processing per plural blocks which can be stored in the data cache. Intermediate data in units of plural blocks is stored in the data cache to be input data to a reconfigured circuit and intermediate data as the result of the processing by the reconfigured circuit is overwritten to the data cache. When the processing of the plural circuits is finished, the result of the processing is output to an external device without being stored in the data cache.

Abstract: There is disclosed a data processor comprising: 1) an instruction execution pipeline comprising N processing stages for executing a load instruction; 2) a status register for storing a modifiable configuration value, the modifiable configuration value having a first value indicating the data processor is capable of executing a misaligned access handling routine and a second value indicating the data processor is not capable of executing a misaligned access handling routine; 3) a misalignment detection circuit for determining if the load instruction performs a misaligned access to a target address of the load instruction and, in response to a determination that the load instruction does perform a misaligned access, generating a misalignment flag; and 4) exception control circuitry capable of detecting the misalignment flag and in response thereto determining if the modifiable configuration value is equal to the first value.

Abstract: A programmable processing system includes a first processor for executing a first portion of an instruction, a second processor for executing a second portion of the instruction, where the second portion of the instruction is interpreted by the first processor as an extension to an immediate operand field included in the first portion of the instruction.