Abstract: A branch prediction method includes the step of retrieving prediction values from a local branch history table and a global branch history table. A branch prediction operation is selectively performed using the value retrieved from the local branch history table when the value from the local branch history table falls within first predicted limits. A branch prediction operation is selectively performed using the value retrieved from the global branch history table when the value from the global branch history falls within a second predetermined limit.

Abstract: A method and system for utilizing bits in a collection of illegal op codes in order to enable pre-decoded instructions to be stored in an instruction cache without increasing the number of bits required to represent the pre-decoded instructions. Upon fetching an instruction from memory, the op code is examined for membership in a collection of illegal op codes. If the instruction op code is a member of this collection, the instruction may be re-encoded to use a different, common illegal op code. If the instruction op code is not a member of the collection of illegal op codes, but is instead an instruction to be stored in the instruction cache in a pre-decoded format, the additional pre-decoded information may be stored in the instruction encoding by utilizing the portion of the op code space which has been vacated by the re-encoding of the illegal op codes.

Abstract: A compiler and vector data transfer instructions for use in a vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. The compiler identifies the use of vector data in an application program and implements one or more vector instructions for transferring the vector data between memory and registers used to perform calculations on the vector data. A vector is partitioned by the compiler into variable-sized streams which are transferred into and out of the processor as burst transactions. The compiler schedules transfers of vector streams required in a calculation so that calculations on a portion of the vector data are performed while a subsequent portion of the vector data is transferred. A vector buffer pool is partitioned into one or more vector buffers and each vector buffer is used at a specific time.

Abstract: A unified buffer, comprising a shifting queue, receives instructions to be tracked by receiving units in a computer architecture. The receiving units search the unified buffer from the oldest entry to the most recent entry. Status bits in each entry indicate which of the receiving unit(s) the entry is destined for. Existing entries in the unified buffer shift down when a new entry is inserted at the top. Entries may be passed to different receiving units by updating the status bits; and an entry expires after it has been accepted by its final receiving unit.

Abstract: A radio card sized for insertion into an electronic device. The radio card includes a housing; a radio circuit disposed within the housing; an internal antenna coupled to the radio circuit; at least one external antenna contact, disposed on the housing, coupled to the radio circuit; an electrical interface, disposed on the housing at a location physically separate from that of the at least one external antenna contact; and the at least one external antenna contact and the electrical interface automatically engaging the electronic device upon insertion of the radio card into the electronic device.

Abstract: Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.

Abstract: The present invention relates to a pipeline microprocessor (MP) comprising a first pipeline stage (ST1) comprising means IPC, MMU, PC, B2, DEC1) for reading and decoding instructions (CODEOP, ADRs, ADRd) of a program recorded in a memory (MEM), and a second pipeline stage (ST2), contiguous to the first pipeline stage, comprising two sectors (ST21, ST22) activated one after the other during complementary half-cycles of a clock signal (H1) of the microprocessor. The first sector reads data contained in two registers (Rd, Rs) of a bank of registers (BANK1, BANK2) of the microprocessor and carries out an operation on the data according to an instruction (CODEOP, ADRs, ADRd) received at the previous clock cycle. The second sector (ST22) comprises means (B4, DEC1) to record the result of the operation in a register of the bank of registers (BANK1, BANK2). Application especially to chip cards.

Abstract: An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results.

Abstract: An Instruction Pointer (IP) signal is received comprising an IP tag field and an IP set field. A plurality of entries corresponding to the IP set field are read, each of the entries comprising an entry tag, an entry bank, and entry data. Each entry tag and entry bank is then compared with the IP tag and each of the plurality of banks. In one embodiment, the IP tag is concatenated with a number representing one of the plurality of banks and compared to the entry tag and entry bank. Separate comparisons may then be performed for each of the other banks.

Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The interface groups signals that together comprises all the necessary information for a coprocessor to issue and execute instructions. Multiple issue groups are formed where each group supports different types of instructions, such as arithmetic instructions, or data transfer instructions. The coprocessor interface has an instruction transfer signal group for transferring different instructions from the CPU to the multi-issue coprocessor, sequentially or in parallel, an issue group designator for specifying an issue path within the multi-issue coprocessor for execution of the instructions, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instructions, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel.

Abstract: A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control logic. The behavior of the memory component, and in particular the selection of a burst transfer format, is controllable via configuration register bits in the one or more configuration registers. Specifically, based on a format selection specified by the configuration bits, the control logic determines the sequence-length of the data transfers between the RAM and the external master. Other than the sequence-length, the data is not otherwise altered during the data transfers.

Abstract: A method and apparatus for harvesting problematic code sections that may cause a hang condition based on a hardware design flaw is presented. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, steps are employed by hardware and/or software to recover from a hang condition, such as flushing instructions dispatched to the plurality of execution units. Upon successful completion of hang recovery, a debug interrupt is injected, causing a debug interrupt handler to be immediately involved before the resumption of normal execution. The debug interrupt handler may then harvest problematic code sections in the undisturbed execution error that may have caused the hang condition.

Abstract: A processing engine 10 for executing instructions in parallel comprises an instruction buffer 600 for holding at least two instructions, with the first instruction 602 in a first position and the second instruction 604 in a second position. A first decoder 612 provides decoding of the first instruction and generates first control signals. The first control signals include first resource control signals, first address generation control signals, and a first validity signal indicative of the validity of the first instruction in the first position. A second decoder 614 provides decoding of the second instruction and generates second control signals. The second control signals include second resource control signals, second address generation control signals, and a second validity signal indicative of the validity of the second instruction in the second position.

Abstract: A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing a burst transfer include determining the starting address of the vector data to be transferred, the ending address of the vector data to be transferred, and whether the ending address of the vector data to be transferred is within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined based on the number of data elements to be transferred, the stride of the vector data to be transferred, and the width of the vector data elements to be transferred. When the amount of data to be transferred is divisible by a factor of two, the multiplication of the stride and width of the data elements is carried out by shifting.

Abstract: An information control pipeline (13) parallels the processor's instruction pipeline (3), contains digital control information in respect of the instruction placed in the instruction pipeline and accompanies that instruction until all component operations prescribed within the instruction have been executed. When at the end of the pipeline, the instruction is presented for execution to a respective functional execution unit (7) of the processor, the respective functional execution unit accesses and uses the control information as a condition to instruction execution. Depending upon the processor, the control information may contain one or more bits, referred to as enable bits, as may be set enabled, indicating that an associated operation in the instruction is to be executed, or by software set disabled, indicating that the associated operation is masked, such as by an exception handler (9) when returning from a resolved exception.

Abstract: A method is disclosed in which a higher level instruction having an immediate is read from memory and translated into two lower level instructions. The first is to move a first portion of the immediate to a register, and the second includes a pointer to the register as well as a second portion of the immediate.

Abstract: An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to branch target addresses, and the PTB includes records that map branch target addresses to subsequent branch target addresses. When a branch instruction is encountered, the BTB can predict the dynamically adjacent subsequent block entry location as the branch target address in the record that also includes the branch instruction address. The PTB can predict multiple subsequent blocks by mapping the branch target address to subsequent dynamic blocks. The PSB holds instructions prefetched from subsequent blocks predicted by the PTB.

Abstract: A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is very small, which has positive effects on the space required and the configuration speed. Broadcasting is supported through the internal bus systems in order to distribute large volumes of data rapidly and efficiently. The ALU is equipped with a power-saving mode to shut down power consumption completely. There is also a clock rate divider which makes it possible to operate the ALU at a slower clock rate. Special mechanisms are available for feedback on the internal states to the external controllers.

Abstract: A method for modifying operating conditions within a computer which translates instructions from a target instruction set to a host instruction set including the steps of monitoring an event occurring within a component of the computer, counting events occurring within a selected interval, generating an exception if a total of events within the selected interval exceeds a prescribed limit, and responding to the exception by modifying a translated sequence of host instructions.

Abstract: Generally, the present invention provides a system and method for processing instructions of a computer program and for indicating instruction attribute and/or status information so that the efficiency of the processing system may be increased. In architecture, the system of the present invention utilizes a pipeline, a scoreboard, and hazard detection circuitry. The pipeline processes and executes instructions of a computer program. Many of the instructions include register identifiers that identify registers where data should be written when the instructions are executed. When the data produced by execution of one of the instructions has yet to be written to the register identified by the one instruction's register identifier and is unavailable for use in executing other instructions of the program, the one instruction's register identifier is transmitted to the scoreboard.