Abstract: An apparatus for and methods of repairing and manufacturing integrated circuits using the apparatus. The apparatus, comprising: a vacuum chamber containing: a movable stage configured to hold a substrate; an inspection and analysis probe; a heat source; a gas injector; and a gas manifold connecting multiple gas sources to the gas injector.

Abstract: Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives.

Abstract: The disclosure relates to a method for making a metal nanowire film. The method includes applying a metal layer on a substrate; placing a carbon nanotube composite structure on the metal layer, wherein the carbon nanotube composite structure defines a number of openings and parts of the metal layer are exposed by the number of openings; dry etching the metal layer using the carbon nanotube composite structure as a mask; and removing the carbon nanotube composite structure. The carbon nanotube composite structure includes a carbon nanotube structure and a protective layer coated on the carbon nanotube structure. The carbon nanotube structure includes a number of carbon nanotubes arranged substantially along the same direction.

Abstract: A substrate having an insulating layer including an oxide is loaded into a chamber, and at least a part of the insulating layer is removed by injecting a process gas including an etching source gas into the chamber. The removal process is performed in a pulse type in which a first period and a second period are repeated a plurality of times. The etching source gas is supplied at a first flow rate during the first period and is supplied at a second flow rate less than the first flow rate during the second period. A temperature of the inside of the chamber remains at 100° C. or more during the removal process.

Abstract: A method of etching silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using anhydrous vapor-phase HF. The HF is combined with an additional precursor in the substrate processing region. The HF may enter through one channel(s) and the additional precursor may flow through another channel(s) prior to forming the combination. The combination may be formed near the substrate. The silicon oxide etch selectivity relative to silicon nitride from is selectable from about one to several hundred. In all cases, the etch rate of exposed silicon, if present, is negligible. No precursors are excited in any plasma either outside or inside the substrate processing region according to embodiments. The additional precursor may be a nitrogen-and-hydrogen-containing precursor such as ammonia.

Abstract: A method for forming at least one Ag or Ag based alloy feature in an integrated circuit, including providing a blanket layer of Ag or Ag based alloy in a multi-layer structure on a substrate. The method further includes providing a hard mask layer over the blanket layer of Ag or Ag based alloy. The method further includes performing an etch of the blanket layer of Ag or Ag based alloy, wherein a portion of the blanket layer of Ag or Ag based alloy that remains after the etch forms one or more conductive lines. The method further includes forming a liner that surrounds the one or more conductive lines. The method further includes depositing a dielectric layer on the multi-layer structure.

Abstract: A process for edge isolation or texture smoothing of a substrate, in which a process medium which allows control treatment of limited regions of the substrate is used. The process is therefore particularly suitable for one-sided treatment of substrates. The viscosity of the process medium plays a central role here. Furthermore, an apparatus designed for the process is presented.

Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.

Abstract: Compositions useful for the selective removal of titanium nitride and/or photoresist etch residue materials relative to metal conducting, e.g., tungsten, and insulating materials from a microelectronic device having same thereon. The removal compositions contain at least one oxidant and one etchant, may contain various corrosion inhibitors to ensure selectivity.

Abstract: An etching method is provided for performing an etching process on an etching target film arranged on a substrate. The etching method includes the steps of supplying a treatment gas including a halogen-containing gas, hydrogen gas, an inert gas, and oxygen gas; performing a treatment on a patterned mask arranged on the etching target film using a plasma generated from the treatment gas; and etching the etching target film that has undergone the treatment using a plasma generated from an etching gas.

Abstract: Provided are methods for etching films comprising transition metals which help to minimize higher etch rates at the grain boundaries of polycrystalline materials. Certain methods pertain to amorphization of the polycrystalline material, other pertain to plasma treatments, and yet other pertain to the use of small doses of halide transfer agents in the etch process.

Abstract: A method for making patterns on a substrate, includes forming an assembly guide on first and second areas of the substrate, the assembly guide having, compared to a reference surface, openings with an opening ratio in the first area greater than that of the second area; depositing a block copolymer layer on the substrate to entirely fill the assembly guide and form an over-thickness on the reference surface; assembling the block copolymer, resulting in an organised portion of the block copolymer layer inside the openings; thinning uniformly the block copolymer layer, until a thickness corresponding to the organised portion of the block copolymer layer is reached; eliminating one of the phases of the assembled block copolymer, resulting in a plurality of initial patterns extending into the layer of block copolymer; and transferring the initial patterns of the block copolymer layer into the substrate to form the final patterns.

Abstract: Slurry composition and a method of substrate polishing used in chemical mechanical polishing (CMP). The present invention concerns a slurry composition containing a polishing agent and a water soluble polymer. The slurry composition contains a water soluble polymer that has a solubility parameter in the range of 9.0 to 14.0 and that may contain hetero atoms at a level sufficient to lower the polishing rate near the edges of the polished substrate defined as the region within 1 mm of the outer edge of the polished substrate to a level below the mean polishing rate of the polished substrate. The water soluble polymer may have a mean molecular weight in the range of 200 to about 3,000,000, and the mean molecular weight may be in the range of 200 to 110,000 if hetero atoms are present in the main-chain structure and the SP value is under 9.5.

Abstract: The invention provides a chemical-mechanical polishing composition that contains (a) abrasive particles, (b) an azole compound having an octanol-water log P of about 1 to about 2, (c) a cobalt corrosion inhibitor, wherein the cobalt corrosion inhibitor comprises an anionic head group and a C8-C14 aliphatic tail group, (d) a cobalt accelerator, (e) an oxidizing agent that oxidizes cobalt, and (f) water, wherein the polishing composition has a pH of about 3 to about 8.5. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate contains cobalt.

Abstract: An etching method using plasma includes generating plasma by supplying process gases to at least one remote plasma source (RPS) and applying power to the at least one RPS, and etching an etching object by supplying water (H2O) and the plasma to a process chamber.

Abstract: A substrate processing method can remove a part of a processing target film formed on a surface of a substrate W under a normal pressure atmosphere while suppressing an influence upon the substrate. A source material of the processing target film, which is decomposed by irradiating an ultraviolet ray thereto under an oxygen-containing atmosphere, is coated on the substrate W, and the processing target film is formed by heating the source material coated on the substrate W. Then, the substrate W having thereon the processing target film is placed within a processing chamber under the oxygen-containing atmosphere where a gas flow velocity is equal to or smaller than 10 cm/sec, and the part of the processing target film is removed by irradiating the ultraviolet ray to the substrate W.

Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

Abstract: A plasma processing method is provided for reducing dimensions of a film to be etched from patterned dimensions, and is capable of reducing dimensions without causing deformation or collapse of the film to be etched. A plasma processing method for trimming a tantalum film by plasma etching using a resist, an antireflective film disposed under the resist, and a mask film disposed under the antireflective film, includes the steps of trimming the antireflective film and the mask film by plasma etching with the resist as a mask; removing the resist and the antireflective film subjected to the trimming, by plasma; and trimming the tantalum film by plasma etching with a mask film obtained after the resist and the antireflective film subjected to the trimming are removed by plasma, as a mask.

Abstract: [Problem] Provided is a polishing composition that can sufficiently maintain a high polishing rate for a barrier layer and an insulating film and suppress the occurrence of a surface defect such as erosion or fang. [Solution] Provided is a polishing composition which is used in the application to polish a polishing object having a barrier layer, a metal wiring layer and an insulating film, the polishing composition including abrasive grains, an oxidant, a metal corrosion inhibitor, a pH adjusting agent and water, in which an aspect ratio of abrasive grains is 1.22 or less and a ratio D90/D10 of a diameter D90 of particles when a cumulative particle weight from the fine particle side reaches 90% of the total particle weight to a diameter D10 of particles when the cumulative particle weight from the fine particle side reaches 10% of the total particle weight of the entire particles is 1.5 or more in a particle size distribution of the abrasive grains determined by a laser diffraction scattering method.

Abstract: The present invention provides a method for fabricating slanted copper nanorods. The method includes manufacturing a workpiece configured to include an etch stop layer on a wafer, placing the workpiece in a slanted position, and etching the slanted workpiece, forming a copper (Cu) layer on the slanted workpiece by plating, removing an over-plated portion from the copper layer, and removing a polysilicon (poly Si) excluding copper from the surface of the workpiece. According to the invention, copper nanorod structures having a uniform array can be fabricated in a large area at a high process yield compared to conventional methods. In addition, the angle and diameter of copper nanorods can be controlled as desired so that the applicability thereof can be greatly increased. Moreover, the present invention can be applied to processes for fabricating various devices, including semiconductor devices, MEMSs (microelectromechanical systems), optical devices, gas sensors, display devices, etc.