Abstract: Methods and systems to perform a computer task in a reduced power consumption state, including to virtualize physical resources with respect to an operating environment and service environment, to exit the operating environment and enter the service environment, to place a first set of one or more of the physical resources in a reduced power consumption state, and to perform a task in the service environment utilizing a processor and a second set of one or more of the physical resources. A physical resource may be assigned to an operating environment upon an initialization of the operating environment, and re-assigned to the service environment to be utilized by the service environment while other physical resources are placed in a reduced power consumption state.

Abstract: Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.

Abstract: Methods, systems, and computer program products are provided for generating application-aware data partitioning to support parallel computing. A label for a user defined data partitioning (UDP) key is generated by a labeling process to configure data partitions of original data. The UDP is labeled by the labeling process to include at least one key property excluded from the original data. The data partitions are evenly distributed to co-locate and balance the data partitions and corresponding computations performed by computational servers. A data record of the data partitions is retrieved by performing an all-node parallel search of the computational servers using the UDP key.

Abstract: An intelligent prediction approach populates and depopulates multiple applications at the system level across applications. The detection and management of user behavior patterns anticipates the user's next request and relates dynamically to user behavior and where that user behavior changes to adjust so as to more accurately set forth a desired result for a user of the present invention.

Abstract: Local storage may be allocated for each processing resource in a process of a computer system. Each processing resource may be virtualized and may have a one-to-one or a many-to-one correspondence with with physical processors. The contents of each local storage persist across various execution contexts that are executed by a corresponding processing resource. Each local storage may be accessed without synchronization (e.g., locks) by each execution context that is executed on a corresponding processing resource. The local storages provide the ability to segment data and store and access the data without synchronization. The local storages may be used to implement lock-free techniques such as a generalized reduction where a set of values is combined through an associative operator.

Abstract: An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution of the loop. The performance information may be used to determine whether to operate the apparatus in a very long instruction word (VLIW) mode or in a coarse grained array (CGA) mode.

Abstract: A system and associated method for mutually exclusively executing a critical section by a process in a computer system. The critical section accessing a shared resource is controlled by a lock. The method measures a detection time when a lock contention is detected, a wait time representing a duration of wait for the lock at each failed attempt to acquire the lock, and a delay representing a total lapse of time from the detection time till the lock is acquired. The delay is logged and used to calculate an average delay, which is compared with a suspension overhead time of the computer system to determine whether to spin or to suspend the process while waiting for the lock to be released. The number of processes waiting for the lock and the number of processes suspended are respectively counted to optimize the method.

Abstract: A data processing circuit is described that includes an instruction decoder operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of multiple functional units, and in the second instruction mode instructions controlling only one functional unit. A mode control circuit controls selecting the instruction modes. The instruction decoder uses time-stationary decoding of operations and destination registers. When instructions are scheduled, constraints are imposed on operations for which operation selection and destination register selection are included on different sides of an instruction mode change. When an instruction containing a jump is encountered, the mode control circuit sets the instruction mode for subsequent instructions in conformity with information provided by executing the jump command.

Abstract: An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software.

Abstract: A technique to perform three-source instructions. At least one embodiment of the invention relates to converting a three-source instruction into at least two instructions identifying no more than two source values.

Abstract: One embodiment of the present invention is a method for a virtual machine to access data from a virtual device, the method including: (a) attaching the virtual device to the virtual machine with a backing store that is a virtual image of a file system conforming to a predetermined file system format, wherein: (i) file system data is stored in one or more files, (ii) the virtual image includes metadata stored apart from the file system data, which metadata corresponds to the predetermined file system format, (iii) the metadata includes one or more directory records, and (iv) the one or more directory records include information that points directly or indirectly to the file system data; (b) issuing a read request for a block of data from the file system as if stored in the predetermined file system format; (c) accessing the metadata and determining the location of the requested block of data in the file system data; and (d) retrieving the requested block of data from the file system data.

Abstract: A virtual-machine-based system provides a mechanism to implement application file I/O operations of protected data by implementing the I/O operations semantics in a shim layer with memory-mapped regions. The semantics of these I/O operations are emulated in a shim layer with memory-mapped regions by using a mapping between a process' address space and a file or shared memory object. Data that is protected from viewing by a guest OS running in a virtual machine may nonetheless be accessed by the process.

Abstract: A branch prediction circuit includes: a memory for storing information representing a branch instruction and a branch prediction; a control circuit for controlling rewriting information in the memory in accordance with a result of determining whether or not a predicted branch has been taken, and determining an attribute of the predicted branch from a branch condition set by the branch instruction and the predicted branch that has been taken, if the predicted branch has been taken; and a rewriting circuit rewriting the information in the memory under the control of the control circuit.

Abstract: A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.

Abstract: A method and system for prefetching in computer system are provided. The method in one aspect includes using a prefetch engine to perform prefetch instructions and to translate unmapped data. Misses to address translations during the prefetch are handled and resolved. The method also includes storing the resolved translations in a respective cache translation table. A system for prefetching in one aspect includes a prefetch engine operable to receive instructions to prefetch data from the main memory. The prefetch engine is also operable to search cache address translation for prefetch data and perform address mapping translation, if the prefetch data is unmapped. The prefetch engine is further operable to prefetch the data and store the address mapping in one or more cache memory, if the data is unmapped.

Abstract: A method for fast remote communication and computation between processors is provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.

Abstract: A method and apparatus for branch determination is disclosed. The method includes a first command issuing within a computer processor. Execution of the first command by the computer processor includes evaluating one or more conditions to set one or more flags. Subsequent to the first command issuing, a second command is issued and executed. Execution of the second command includes causing the computer processor to wait until the one or more flags are set. Subsequent to the first and second commands issuing, a third command is issued and executed. Execution of the third command includes performing a jump operation based on a value of at least one of the one or more flags set by the first command.

Abstract: Selective power control of one or more processing elements matches a degree of parallelism to requirements of a task performed in a highly parallel programmable data processor. For example, when program operations require less than the full width of the data path, a software instruction of the program sets a mode of operation requiring a subset of the parallel processing capacity. At least one parallel processing element, that is not needed, can be shut down to conserve power. At a later time, when the added capacity is needed, execution of another software instruction sets the mode of operation to that of the wider data path, typically the full width, and the mode change reactivates the previously shut-down processing element.

Abstract: A computer program product, apparatus and method for negating initiative for select entries from a shared, strictly FIFO initiative queue in a multi-tasking multi-processor environment. An exemplary embodiment includes a computer program product for negating initiative for select entries from a shared initiative queue in a multi-tasking multi-processor environment, the computer program product including a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method including identifying an element within the environment that has failed and recovered, not removing the element from the shared initiative queue and entering a boundary element entry into the shared initiative queue.

Abstract: A computer, circuit, and computer-readable medium are disclosed. In one embodiment, the processor includes an instruction decoder unit that can decode a macro instruction into at least one micro-operation with a set of data fields. The resulting micro-operation has at least one data field that is in a compressed form. The instruction decoder unit has storage that can store the micro-operation with the compressed-form data field. The instruction decoder unit also has extraction logic that is capable of extracting the compressed-form data field into an uncompressed-form data field. After extraction, the instruction decoder unit also can send the micro-operation with the extracted uncompressed-form data field to an execution unit. The computer also includes an execution unit capable of executing the sent micro-operation.