Abstract: The present invention provides a Group III nitride semiconductor light-emitting device which exhibits improved light emission efficiency. The light-emitting layer has a MQW structure in which a plurality of layer units are repeatedly deposited, each layer unit comprising a well layer, a capping layer, and a barrier layer sequentially deposited. The well layer is formed of InGaN, the capping layer has a structure in which a GaN layer and an AlGaN layer are deposited in this order on the well layer, and the barrier layer is formed of AlGaN. The AlGaN layer has a higher Al composition ratio than that of the barrier layer. The AlGaN layer in the former portion has a lower Al composition ratio than that of the AlGaN layer in the latter portion when the light-emitting layer is divided into a former portion at the n-cladding layer side and a latter portion at the p-cladding layer side in a thickness direction.

Abstract: Device and a method of forming a device are disclosed. The method includes providing a crystalline-on-insulator (COI) substrate. The COI substrate includes at least a base substrate over a buried insulator layer. Through via (TV) contacts are formed within the substrate. The TV contact extends from a top surface of the base substrate to within the buried insulator layer. Upper interconnect levels are formed over the top surface of the base substrate. A lower redistribution (RDL) is formed over a bottom surface of the base substrate. The buried insulator layer corresponds to a first RDL dielectric layer of the lower RDL and protects the sidewalls of the TV contacts.

Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate having an active region defined by an isolation layer, a gate line defining a bit line contact region in the active region and extending in one direction, and a dielectric layer covering the semiconductor substrate and the gate line formed in the semiconductor substrate. The semiconductor device is provided with a bit line contact hole formed in the dielectric layer and exposing the bit line contact region. In order to alleviate a self-aligned contact (SAC) fails caused by a conductive material remaining in a contact hole, the semiconductor device contains a bit line contact spaced apart from a sidewall of the bit line contact hole and formed in the bit line contact hole.

Abstract: A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL.

Abstract: According to an aspect of the present invention, an organic luminescence display includes a substrate, a first electrode on the substrate, a pixel defining layer on the first electrode and partially exposing the first electrode, an auxiliary layer on the pixel defining layer, an organic layer on the first electrode and an edge of the auxiliary layer, and a second electrode on the organic layer.

Abstract: The present invention relates to light emitting diodes comprising at least one nanowire. The LED according to the invention is an upstanding nanostructure with the nanowire protruding from a substrate. A bulb with a larger diameter than the nanowire is arranged in connection to the nanowire and at an elevated position with regards to the substrate. A pn-junction is formed by the combination of the bulb and the nanowire resulting in an active region to produce light.

Abstract: In a method of manufacturing a semiconductor device, a first semiconductor element is mounted on a carrier. A b-stage curable polymer is deposited on the carrier. A second semiconductor element is affixed on the polymer.

Abstract: A transfer-bonding method for light emitting devices including following steps is provided. A plurality of light emitting devices is formed over a first substrate and is arranged in array, wherein each of the light emitting devices includes a device layer and an interlayer sandwiched between the device layer and the first substrate. A protective layer is formed over the first substrate to selectively cover parts of the light emitting devices, and other parts of the light emitting devices are uncovered by the protective layer. The device layers uncovered by the protective layer are bonded with a second substrate. The interlayers uncovered by the protective layer are removed, so that parts of the device layers uncovered by the protective layer are separated from the first substrate and are transfer-bonded to the second substrate.

Abstract: Provided are a light emitting device and a light emitting device package including the same. The light emitting device comprises a first conductive type semiconductor layer, an active layer comprising a plurality of quantum well layers and a plurality of barrier layers, which are alternately laminated on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the active layer. The plurality of barrier layers comprise a plurality of first barrier layers comprising an n-type dopant, and the conductive type dopant doped into the plurality of first barrier layers have different doping concentrations for each layer.

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The ReRAM cells may include a first layer operable as a bottom electrode and a second layer operable to switch between a first resistive state and a second resistive state. The ReRAM cells may include a third layer that includes a material having a lower breakdown voltage than the second layer and further includes a conductive path created by electrical breakdown. The third layer may include any of tantalum oxide, titanium oxide, and zirconium oxide. Moreover, the third layer may include a binary nitride or a ternary nitride. The binary nitrides may include any of tantalum, titanium, tungsten, and molybdenum. The ternary nitrides may include silicon or aluminum and any of tantalum, titanium, tungsten, and molybdenum. The ReRAM cells may further include a fourth layer operable as a top electrode.

Abstract: A micromechanical functional apparatus, particularly a loudspeaker apparatus, includes a substrate having a top and an underside and at least one circuit chip mounted on the underside in a first cavity. The apparatus further includes a micromechanical functional arrangement, particularly a loudspeaker arrangement, having a plurality of micromechanical loudspeakers mounted on the top in a second cavity. A covering device is mounted above the micromechanical functional arrangement on the top. An appropriate method is implemented to manufacture the micromechanical functional apparatus.

Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.

Abstract: Isolation structures for isolating semiconductor devices from a substrate include floor isolation regions buried within the substrate and one or more trenches extending from a surface of the substrate to the buried floor isolation region.

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The resistive switching nonvolatile memory cells may include a first layer disposed. The first layer may be operable as a bottom electrode. The resistive switching nonvolatile memory cells may also include a second layer disposed over the first layer. The second layer may be operable as a resistive switching layer that is configured to switch between a first resistive state and a second resistive state. The resistive switching nonvolatile memory cells may include a third layer disposed over the second layer. The third layer may be operable as a resistive layer that is configured to determine, at least in part, an electrical resistivity of the resistive switching nonvolatile memory element. The third layer may include a semi-metallic material. The resistive switching nonvolatile memory cells may include a fourth layer that may be operable as a top electrode.

Abstract: An array or moat isolation structure for eDRAM with heterogeneous deep trench fill and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method further includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method further includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method further includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method further includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.

Abstract: A TFT array substrate includes a plurality of pixels arranged in a matrix, in which the pixel includes a thin film transistor, a pixel electrode conductively connected to a drain electrode, and a common electrode that is formed opposite the pixel electrode with an insulation film interposed therebetween. In the TFT array substrate, when one of the pixels is focused, the pixel electrode is divided into a plurality of divided pixel electrodes and includes a plurality of branch conductive parts that conductively connect each of the drain electrode and the plurality of divided pixel electrodes, and in plane view, the common electrode is not formed in at least a part of a formation region of the plurality of branch conductive parts.

Abstract: An integrated circuit (IC) is provided where the IC includes a first die, a second die stacked above the first die, and a plurality of die-to-die interconnects coupling the first die to the second die, where the plurality of die-to-die interconnects includes at least one redundancy die-to-die interconnect. In one implementation, the plurality of die-to-die interconnects includes a plurality of pre-designated die-to-die interconnects, where if a pre-designated die-to-die interconnect of the plurality of pre-designated die-to-die interconnects is defective, then signals intended for transmission via the pre-designated die-to-die interconnect are instead transmitted via the at least one redundancy die-to-die interconnect.

Abstract: A light-emitting diode (LED) structure and a method for manufacturing the LED structure are disclosed for promoting the recognition rate of LED chips, wherein a roughness degree of the surface under a first electrode pad of a first conductivity type is made similar to that of the surface under a second electrode pad of a second conductivity type, so that the luster shown from the first electrode pad can be similar to that from the second electrode pad, thus resolving the poor recognition problem of wire-bonding machines caused by different lusters from the first and second electrode pads.

Abstract: A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip.