Abstract: A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

Abstract: A gate cavity is formed exposing a portion of a silicon fin by removing a sacrificial gate structure that straddles the silicon fin. An epitaxial silicon germanium alloy layer is formed within the gate cavity and on the exposed portion of the silicon fin. Thermal mixing or thermal condensation is performed to convert the exposed portion of the silicon fin into a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions. A functional gate structure is formed within the gate cavity providing a finFET structure having a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions.

Abstract: A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.

Abstract: According to example embodiments, a nonvolatile memory cell includes a first electrode and a second electrode, a resistance change film between the first electrode and the second electrode, and a first barrier film contacting the second electrode. The resist change film contains oxygen ions and contacts the first electrode. The first barrier film is configured to reduce (and/or block) the outflow of the oxygen ions from the resistance change film.

Abstract: A method of manufacturing a light generating device and a light generating device manufactured through the method are disclosed. The method of manufacturing a light generating device according to an exemplary embodiment of the present invention, includes preparing a semiconductor stacking structure including a p-type semiconductor layer, an n-type semiconductor layer and an active layer disposed between the p-type semiconductor layer and the n-type semiconductor layer; forming a metal thin film on the n-type semiconductor layer or on the p-type semiconductor layer; annealing the metal thin film to form a grain boundary at the metal thin film; applying liquid with graphite powder to the metal thin film with the grain boundary; thermally treating the semiconductor stacking structure to which the liquid with graphite powder is applied; and removing the metal thin film with the grain boundary.

Abstract: A light emitting device includes a light emitting layer, a substrate that is transparent to an emission wavelength of the light emitting layer and positioned to receive an emission wavelength from the light emitting layer, a convex pattern including a collection of a plurality of convex portions discretely arranged on a front surface of the substrate with a first pitch, an n type nitride semiconductor layer located on the front surface of the substrate to cover the convex pattern and a p type nitride semiconductor layer located on the light emitting layer. The light emitting layer is located on the n type semiconductor layer. Each of the convex portions includes a sub convex pattern comprising a plurality of fine convex portions discretely formed at the top of the convex portion with a second pitch smaller than the first pitch, and a base supporting the sub convex pattern.

Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Abstract: A thin film transistor (TFT) is provided, which includes a substrate, a first gate layer, an insulation layer, a first source/drain layer, a second source/drain layer, a semiconductor layer, a passivation layer and a second gate layer. The first gate layer is disposed on the substrate. The insulation layer is disposed on the first gate layer. The first source/drain layer is disposed on the insulation layer. The second source/drain layer is disposed on the insulation layer. The semiconductor layer is disposed on the insulation layer and covers the first source/drain layer and the second source/drain layer. The passivation layer is disposed on the insulation layer and covers the semiconductor layer. The second gate layer is disposed on the passivation layer and contacts the first gate layer through a via so that the two gate layers keep a same voltage level.

Abstract: Light emitting devices, packages and related methods are disclosed with electrical leads with one or more indicators. A package can include a leadframe that can include at least a first lead and a second lead. The first lead can include a first end for electrical connection to at least one light emitting device and a second end extending toward a first side of the package. The second lead can include a first end for electrical connection to at least one light emitting device and a second end extending toward a second side of the package. One or both of the second end of the first lead or the second end of the second lead can comprise an indicator serving as an identifier.

Abstract: A semiconductor device is provided that includes a substrate including a device region and a peripheral region surrounding the device region, a first interconnection including one or more first conductive lines extending in a first direction, a second interconnection including one or more second conductive lines extending in the first direction, the second interconnection spaced apart from the first interconnection, a first conductive plate and a second conductive plate spaced apart from each other, the first conductive plate corresponding to the first interconnection and the second conductive plate corresponding to the second interconnection, one or more first vias connecting the first conductive lines to the first conductive plate and overlapping the device region and one or more second vias connecting the second conductive lines to the second conductive plate, the second vias overlapping the device region and arranged in a staggered, alternating configuration with the one or more first vias.

Abstract: A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

Abstract: A method of forming a metal silicide region. The method comprises forming a metal material over and in contact with exposed surfaces of a dielectric material and silicon structures protruding from the dielectric material. A capping material is formed over and in contact with the metal material. The silicon structures are exposed to heat to effectuate a multidirectional diffusion of the metal material into the silicon structures to form a first metal silicide material. The capping material and unreacted portions of the metal material are removed. The silicon structures are exposed to heat to substantially convert the first metal silicide material into a second metal silicide material. A method of semiconductor device fabrication, an array of silicon structures, and a semiconductor device structure are also described.

Abstract: Disclosed herein is an ultraviolet (UV) light emitting device. The light emitting device includes an n-type contact layer including a GaN layer; a p-type contact layer including a GaN layer; and an active layer of a multi-quantum well structure disposed between the n-type contact layer and the p-type contact layer, the active area configured to emit near ultraviolet light at wavelengths of 365 nm to 309 nm.

Abstract: A semiconductor device includes a recess defined in a dielectric layer, the recess having an upper sidewall portion extending to an upper corner of the recess and a lower sidewall portion below the upper sidewall portion. An interconnect structure is positioned in the recess. The interconnect structure includes a continuous liner layer having upper and lower layer portions positioned laterally adjacent to the upper and lower sidewall portions, respectively. The upper layer portion includes an alloy of a first transition metal and a second transition metal and the lower layer portion includes the second transition metal but not the first transition metal. The interconnect structure also includes a fill material substantially filling the recess, wherein the second transition metal has a higher wettability for the fill material than the alloy.

Abstract: A pixel circuit includes a plurality of pixel units, and one of the pixel units includes a photosensor, a readout circuit, and a switch circuit. The readout circuit is coupled to a supply voltage and the photosensor, which includes a floating diffusion node for storing data of the photosensor and an output node for outputting data of the floating diffusion node. The switch circuit is coupled between the photosensor and a tail node, wherein the tail node is coupled to the floating diffusion node of another pixel unit.

Abstract: According to one embodiment, a semiconductor light emitting device includes first and second conductive layers, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting part. The second semiconductor layer is provided between the first conductive layer and the first semiconductor layer. The light emitting part is provided between the first and second semiconductor layers. The second conductive layer is in contact with the second semiconductor layer and the first conductive layer between the second semiconductor layer and the first conductive layer. The first and second conductive layers are transmittable to light emitted from the light emitting part. The first conductive layer includes a polycrystal having a first average grain diameter. The second conductive layer includes a polycrystal having a second average grain diameter of 150 nanometers or less and smaller than the first average grain diameter.

Abstract: A gallium nitride (GaN) device with leakage current-based over-voltage protection is disclosed. The GaN device includes a drain and a source disposed on a semiconductor substrate. The GaN device also includes a first channel region within the semiconductor substrate and between the drain and the source. The GaN device further includes a second channel region within the semiconductor substrate and between the drain and the source. The second channel region has an enhanced drain induced barrier lowering (DIBL) that is greater than the DIBL of the first channel region. As a result, a drain voltage will be safely clamped below a destructive breakdown voltage once a substantial drain current begins to flow through the second channel region.

Abstract: In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench. In a further embodiment, this may provide for a substantially v-shaped opening or entry to the trench for the formation of further layers.

Abstract: A semiconductor light-emitting device including an epitaxial structure, a first electrode structure, a second electrode structure, a light reflective metal layer, a resistivity-enhancing structure and a protection ring is provided. The light-emitting epitaxial structure has a first surface and a second surface. The light-emitting epitaxial structure has a first zone and a second zone. The first electrode structure is disposed within the first zone. The second electrode structure is disposed within the second zone. The light reflective metal layer is disposed adjacent to the second surface. The resistivity-enhancing structure is disposed in contact with a surface of the light reflective metal layer and corresponding to a position of the first electrode structure. The protection ring has a first portion and a second portion. The first portion surrounds a sidewall of the light reflective metal layer. The second portion corresponds to the second electrode structure.

Abstract: A method of fabricating a composite integrated optical device includes providing a substrate comprising a silicon layer, forming a waveguide in the silicon layer, and forming a layer comprising a metal material coupled to the silicon layer. The method also includes providing an optical detector, forming a metal-assisted bond between the metal material and a first portion of the optical detector, forming a direct semiconductor-semiconductor bond between the waveguide, and a second portion of the optical detector.