Abstract: A plurality of signals are mixed in a non-linear waveguide for generating a near field sum frequency output pattern. The near field output pattern is monitored for changes which correspond to changes in the phase relationship between the plurality of signals. A grating provides a mask through which the near field pattern may propagate. Detectors positioned above the grating at predetermined locations measure the intensity of the near field pattern and a change in the phase relationship between the input signals is determined from a change in the intensity of the near field output pattern.

Abstract: Disclosed is an improved bipolar-and-complementary MOS transistor coexisting semiconductor device and a method of making the same. A collector-and-base separator is formed on the site allotted to a bipolar transistor along with a source-and-drain separator on each site allotted to PMOS and NMOS transistors. The superficial collector-and-base separator coating causes no stress to the lattice of the underlying region in the epitaxy of the semiconductor substrate, and therefore there can be no lattice defect which may appear in a conventional composite type semiconductor device structure as a result of selective oxidization of the epitaxial layer to separate the base and collector region of the bipolar transistor. Such a superficial collector-and-base separator according to the present invention assures that the bipolar transistor each of such composite type semiconductor devices is free from the lowering of the breakdown voltage at its collector-and-base junction.

Abstract: Generally, and in one form of the invention, a p-n junction diffusion barrier is disclosed comprising a first semiconductor layer 28 of p-type conductivity, a second semiconductor layer 32 of n-type conductivity and a third semiconductor layer 30 of p-type conductivity disposed between the first and second layers, the third layer being doped with a relatively low diffusivity dopant in order to form a diffusion barrier between the first and the second semiconductor layers.

Abstract: A bipolar transistor having an emitter, a base, and a collector includes an intrinsic base region having narrow side areas and a wider central area. The side areas are located adjacent to the extrinsic base region, while the central area is disposed underneath the emitter. The lateral doping profile of the base is tailored so that the doping concentrations in the extrinsic region and the central area are relatively high compared to the doping concentration of the narrow side areas of the intrinsic base. The combination of the narrow side areas and the lateral base doping profile constrains the depletion region within the base thereby lowering punch-through voltage of the transistor without loss of beta.

Abstract: A solid state, electronic, optical transition device includes a multiple-layer structure of semiconductor material which supports substantially ballistic electron/hole transport at energies above/below the conduction/valance band edge. The multiple layer structure of semiconductor material includes a Fabry-Perot filter element for admitting electrons/holes at a first quasibound energy level above/below the conduction/valance band edge, and for depleting electrons/holes at a second quasibound energy level which is lower/higher than the first energy level. Such an arrangement allows common semiconductor material to be used to produce emitters and detectors and other devices which can operate at any of selected frequencies over a wide range of frequencies.

Abstract: A semiconductor device comprises a bonding pad serving as a power supply terminal and a plurality of bonding pads having the same function and serving as one of grouped terminals other than the power supply terminal.

Abstract: Power and ground connections are provided using or more conductive layers provided in an integrated-circuit package design. A leadframe has either a tape assembly or a heat-conducting dielectric ceramic substrate attached to the die-attach paddle of the leadframe and one or more conductive planes are formed on the top surface of the tape assembly or the ceramic substrate. The tape assembly includes a conductive metal layer, a polyimide layer, and an adhesive layer. The metal layer on the tape or ceramic substrate and the metal die-attach pad of the leadframe are used as low inductance power planes providing connections to the integrated-circuit. No vias are used. Use of a metal die-attach paddle for the leadframe is optional when a ceramic substrate is used.

Abstract: An electronic read-only memory module having an inner casing and an outer casing cap. The inner casing is located on a secondary circuit board from whose edge which projects laterally from the inner casing project contact elements for producing a plug contact with contact counterelements located on a circuit board of a device, which is to be equipped with the ROM module. The outer casing cap has lateral internal gaps which protectively receive the contact elements. Due to the fact that the free ends of the contact elements are set back inwardly with respect to the open edge of the outer casing cap, the contact elements are protected against damage. This also greatly simplifies the loading of a device with the ROM module, because as a result of a simple plugging movement numerous contact elements can be brought into reliable contact with the contact counterelements.

Abstract: A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

Abstract: For enhanced resistance to electromigration failure, a thin metal film interconnect on an integrated circuit chip should use multiple parallel minimum-width lines when the minimum linewidth is less than one and one-half times the mean grain size of the metal film. When the interconnect is longer than a certain predetermined length, then the multiple lines of the interconnect should have intermediate interconnections or bridges between neighboring ones of the multiple lines. When the interconnect is many times longer than the predetermined length, then the bridges define slots between the neighboring lines, and the slots should have a length of about the predetermined length. When the interconnect is many times longer than the predetermined length and the interconnect has more than two parallel lines, then the slots on one side of a parallel line should be staggered or offset with respect to the slots on the other side of the parallel line.

Abstract: A varistor material having a non-linear coefficient of at least 30 and a varistor voltage of at least 800 V/mm is disclosed. The varistor is produced by a method including commingling an admixture of ZnO and a manganese compound while preventing the admixture from contacting with a surface containing an element belonging to group IIIb of the Periodic Table. The resulting mixture is calcined and then pulverized while preventing the contact with a IIIb element-containing surface to obtain a pulverized product having a content of impurity compounds of a IIIb element of not greater than 20 ppm by weight. The pulverized product is molded and sintered at such a temperature as to obtain the varistor formed from particles with an average particle size of not greater than 5 .mu.m.

Abstract: For the manufacture of a power semiconductor module, one proceeds from a ceramic base board on which copper plates and copper conductor paths are fastened by a suitable method. The ceramic base plate is then scratched and broken. As a result, ceramic side boards are produced which are connected to the base board via conductive paths. The side boards are then swung up, as a result of which the conductive paths fastened on the side boards come into a plane above the base plane. By means of suitable, possibly multiple, breaking and folding of the side boards and suitable development of the ends of the conductive paths, the connecting poles of the power semiconductor chips can be directly contacted. Electronic circuits can be arranged on the side boards.

Abstract: An ohmic contact includes a metal boride layer on a semiconducting diamond layer. The metal boride preferably includes boron and a transition metal and, more preferably, a refractory metal. Heating of the metal boride layer and diamond during fabrication forms a highly boron-doped surface portion of the semiconductor diamond by boron diffusion. Alternately, the highly doped surface portion may be formed by selective ion implantation, annealing to form a graphitized surface portion, and removing the graphitized surface portion by etching to thereby expose the highly doped surface portion. The highly doped surface portion lowers the electrical resistivity of the contact. In addition, an interface region of a carbide may also be readily formed by heating. The carbide interface region enhances mechanical adhesion of the metal boride and also serves to lower the electrical resistance of the contact.

Abstract: There is disclosed an FET having a high drain breakdown voltage and a short gate length comprising an active layer 2 formed on a surface layer of a semiconductor substrate 1; a highly doped impurity source region 4 and highly doped impurity drain region 4 formed in the surface layer of the semiconductor substrate 1 to sandwich the active layer 2; an insulation film 5 formed on the highly doped impurity source region 4; a gate electrode 8 formed on the active layer 2 and the insulation film 5 while maintaining a constant distance 1.sub.GD from the highly doped impurity drain region 4; and a source electrode 6 and a drain electrode 7 formed on the highly doped impurity source region 4 and the highly doped impurity drain region 4, respectively.

Abstract: A set of standard materials, which comprises at least two kinds of standard materials, for calibration of a photoelectric colorimeter used for the instrumental measurement of petroleum products for their ASTM color, comprising at least two kinds of standard materials each of which is a mixed solution having a color corresponding to an ASTM color and comprises (a) at least five members selected from the group consisting of seven specific colorants such as 3-methyl-1-phenyl-4-(phenylazo)-pyrazol-5-ol, 1-(phenylazo)-2-naphthalenol and 1-[[4-[(dimethylphenyl)azo]dimethylphenyl]azo]-2-naphthalenol, (b) 1-phenyl-1-xylylethane as a solvent for said colorants, and (c) dodecane as a diluent; and a method for instrumental measurement of petroleum products for their ASTM color by a photoelectric colorimeter, which comprises calibrating the photoelectric colorimeter by the use of said at least two kinds of standard materials.

Abstract: This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance.

Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

Abstract: Disclosed herein is a superconducting field effect transistor (FET) which has at least an active region formed from a film of oxide normal conductor, a plurality of electrodes formed from a film of oxide superconductor, and a means to control the current which flows between the electrodes through the active region. Having a much greater electrode distance than the conventional superconducting device, it can be produced easily by lithography without resorting to special techniques.

Abstract: A polarized-light scatterometer for measuring the thickness of a film coated on the partial of a substrate, the film having a straight line edge on the surface of the substrate coated with the film.

Abstract: An encapsulated microelectronic device (100) including a base (101) and a semiconductor device (305) having a top and a bottom. The bottom is attached to the base (101). The semiconductor device (105) has a thickness in the range from one-fourth to three-fourths of a millimeter and has a bottom metallization consisting of aluminum (407)/chromium (405)/nickel (403)/gold (401). The semiconductor device (305) has a contact (115) attached to the top. The encapsulated microelectronic device (100) has a molded top (120) surrounding the semiconductor device (305). The molded top (120) is made from low stress molding material.