Abstract: A semiconductor integrated circuit comprises a transistor which has a first electrode, a second electrode and a third electrode, said transistor conducting a current of a first power source from the second electrode to the third electrode by a power supplied to the first electrode; a driver to supply said first electrode with power for driving said transistor; a reference voltage circuit to generate a reference voltage which is variable in response to temperature of said transistor, said reference voltage being used as the reference for comparison; a comparative voltage circuit to generate a comparative voltage which is variable in response to a current flowing from said second electrode to said third electrode, said comparative voltage being compared with said reference voltage; and a controller which receives said reference voltage and said comparative voltage and which supplies a control signal to said driver, said control signal being based on a result of the comparison between the comparative voltage and

Abstract: An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad 31 to a first power supply node (76).

Abstract: The present invention is about a mechanism in the a container such as a FIBC, which enables the immediate neutralization of the electrostatic charges generated during filling, emptying or transporting of the containers. FIBCs are used to carry bulk solid powders, such as sugar, flour, starch and chemical substances. The FIBC, which enables neutralization of the electrostatic charge generated within the material in the bag, developed with this invention, is characterized by inner devices knitted preferably with multi-filaments or mono-filaments and tapes, made of polymers in the form of a web or net with a special antistatic additive, established to an appropriate place in the FIBC so as to have maximum contact with the bulk solid powders in the FIBC in order to neutralize the electrostatic charge at distant points of the FIBC's wall.

Abstract: A system and method for dynamically protecting a vulnerable device from an ESD event includes an ESD event sensor and a breakdown voltage adjustment circuit. The ESD event sensor detects an ESD event and provides a signal to the breakdown voltage adjustment circuit indicating that an ESD event has occurred. The breakdown voltage adjustment circuit receives the signal from the ESD event sensor and adjusts the breakdown voltage of the vulnerable device during the ESD event.

Abstract: Disclosed herein is a gated diode overvoltage protection circuit. In one embodiment, the circuit includes: a terminal, a gated diode, and a bias circuit. The terminal is configured to convey a voltage signal. The gated diode has an anode, a cathode, and a gate. The gated diode is coupled between the terminal and a predetermined voltage node so as to enter a forward conduction mode during electrostatic discharge (ESD) events, overvoltage conditions, or transient signal excursions. The bias circuit is configured to establish a low-resistance path between the cathode and gate when the gated diode is in a forward conduction mode, and to eliminate the low-resistance path when the gated diode is not in the forward conduction mode.

Abstract: A resistor is connected in series with a semiconductor laser device, while, on both sides of this resistor, a first capacitor and a second capacitor are connected in parallel with the semiconductor laser device so as to be arranged in ?-type configuration, thereby achieving a high electrostatic breakdown voltage.

Abstract: A control system for a fan of a cooling system of an internal combustion engine of a motor vehicle having a viscous coupling (fan clutch) driving the fan and a control unit (PID governor) to which the setpoint temperature and the measured actual temperature of the cooling system (coolant temperature) are fed. The control unit (PID governor) is connected downstream to a limiter, which holds the ratio of output speed to input speed below a specifiable limit (x % of input speed). An overheat protection logic disables the limiter when the actual coolant temperature exceeds a specifiable critical temperature that is higher than the setpoint temperature of the control unit (PID governor).

Abstract: An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad 31 to a first power supply node (76).

Abstract: A device for detecting failure of a field effect transistor (FET) includes a first FET1 connected in series with a motor M between a power source terminal and ground, a motor control unit 11 for on/off controlling a voltage to be applied to said motor to set normal/reverse operation and stopping of said motor, a gate control unit for on/off controlling a gate voltage to be applied to said FET to control driving of said motor, a voltage applying means VB, R1 for applying a positive voltage at a prescribed voltage level to the current input terminal of the FET; a voltage detecting unit CMP1 for detecting the voltage level of the positive voltage thus applied when said gate voltage is off; and a failure detecting unit 14 for detecting short-circuiting failure of the FET on the basis of a change in the voltage level detected by said voltage detecting unit when said gate voltage is off while said motor stops.

Abstract: An input circuit for an integrated circuit includes an electrostatic discharge circuit. The input circuit incorporates an interconnect pad, an ESD protection resistor, and an interconnect line that are coupled to the active internal components of the integrated circuit. The interconnect pad is coupled to the interconnect line, and the interconnect line is coupled to the ESD protection resistor which is coupled to the active internal components of the integrated circuit. The ESD protection resistor is positioned physically proximate to the active internal components of the integrated circuit and adjusted in value to compensate for the intrinsic resistance or RC time constant of the interconnect line. The circuitry provides for a lower signal propagation delay through the external connection because of lower RC time constants to drive the capacitance of the interconnect.

Abstract: A semiconductor device having an electrostatic discharge protective circuitry adapted to a common discharge line (CDL) is disclosed. In the embodiments of the present invention, semiconductor device includes a plurality of bonding pads, each having at least one connecting terminal, a common discharge line, and a protective device connected between the connecting terminal and the common discharge line. Moreover, the protective device is composed of a silicon-control-rectifier that is used for electrostatic discharge protection and a zener diode for lowering a trigger voltage of the silicon-control-rectifier.

Abstract: The present invention relates to a reverse wiring protection device for ground fault circuit interrupter that includes a tripper and control circuit. The tripper comprises: a pull rod with flat, a L-shaped latch, a balance frame coupled with the latch moving up and down with the pull rod, a trip coil, a plunger and a contact switch (K) which is capable of energizing and de-energizing the trip coil. The reset can't be depressed when an installer or user miswires the line and the load.

Abstract: An arc discharge protection apparatus to prevent arc discharge from occurring in a high voltage output zone caused by abnormal conditions includes an electrode plate to absorb high voltage arc discharge signals released by a voltage boosting unit in the high voltage output zone. A voltage switch unit receives the high voltage arc discharge signals absorbed by the electrode plate and transforms to low voltage arc discharge signals. A rectification unit receives and rectifies the low voltage arc discharge signals and outputs an arc hybrid wave. A trigger unit detects the arc hybrid wave and outputs a trigger signal to stop operation of the control unit or driving unit, thereby prevents arc discharge from causing damage to the surrounding elements resulting from accumulation of heat or sparks.

Abstract: An inrush current limiter circuit (20) includes a mirrored transistor (50) responsive to a control signal (VDRIVE) developed from a sense current (ISENSE), and has a first source (51) coupled to a supply voltage, a common drain (53) that routes a load current (ILOAD) to an output node (45), and a second source that samples the load current to produce the sense current. A fault protection circuit (64) disables the mirrored transistor in response to a first fault condition (TEMP, UVLO) and is coupled to a first lead (43) for externally adjusting a fault threshold. A fault communication circuit (250) is coupled to the first lead to receive a fault signal representative of an external fault condition to disable the mirrored transistor.

Abstract: Systems, methods, and apparatuses for isolating an electrical problem in a power pack include a system in accordance with various embodiments of the invention. The system includes a power pack. The power pack includes an input cord including at least a first indicator, wherein the input cord is adapted to receive electrical current from an electrical source, and further adapted to transmit the electrical current to the power pack, and wherein the first indicator indicates when the input cord transmits electrical current from the electrical source. The power pack also includes a housing including at least a second indicator, wherein the second indicator indicates when the power pack receives electrical current from the input cord.

Abstract: System for surge protection of an object comprising a supply unit, which is connected to the secondary output of an external transformer. The secondary windings (1) of the external transformer are coupled in a star configuration, the star point of the transformer being connected to a downstream neutral conductor (7) and an earth electrode provided near to the transformer. In the supply unit, at least one phase conductor (6) is connected to the neutral conductor (7) by means of a surge protective device of a first type (4), and the neutral conductor (7) is connected to an earth electrode (5) provided near to the supply unit by means of a surge protective device of a second type (9). The surge protective device of the first type (4) comprises a voltage dependent resistor or varistor and the surge protective device of the second type (9) comprises a lightning current arrester or spark gap element.

Abstract: The invention relates to a method for automatically re-closing when there is a short-circuit in a line section of an electric energy supply line, whereby said section is defined by one switch respectively which comprises an allocated short-circuit detection device. According to the inventive method and after the switches have been released by a short-circuit, a re-closing instruction that is produced on the one end of the line section trips the switch on the other end. The aim of the invention is to carry out said method in such a way that the switch is treated with care as far as possible. The switch on the other end of the line section is tripped after a predetermined time delay provided that the short-circuit in the line section terminates during the time delay.

Abstract: A current limiter circuit for limiting current in an electrical circuit element such as the magneto-resistive portion of a read head forming a portion of a hard disk drive and including: a first circuit connected to one end of the circuit element for applying a bias current of a desired value to the circuit element in response to the value to an input signal; a second circuit connected to the other end of the circuit element for setting the amplitude of the voltage signal generated across the circuit element in response to the bias current; and a third electrical circuit connected to both the first and second circuits for limiting the value of bias current to a predetermined level for an abnormal event such as a current surge, a short circuit, or any other type of undesired current operating condition.

Abstract: A limiting circuit for a brushless dc motor in accordance with the present invention comprises a first transistor, a second transistor, a first resistor and a second resistor. The first transistor, the second transistor, the first resistor and the second resistor are arranged in complementary connection to constitute the limiting circuit which has a first terminal connected to a power source and a second terminal connected to a motor drive circuit.

Abstract: The invention relates to a method and arrangement for generating a trigger signal according to the current differential protection principle when a fault occurs on a section of an electrical power supply system, in which differential current values and stabilization current values are detected and monitored with regard to exceeding limit values. A trigger signal is generated if positive results of the instances of monitoring are present. The differential current values and the stabilization current values are calculated with instantaneous values of the detected power supply currents as instantaneous values. A first measurement quantity and a second measurement quantity are formed, and a check is made to determine whether the two measurement quantities exceed a predetermined limit value of the differential quotient of the differential current with respect to time. If the instances of evaluation and the instances of monitoring produce positive results, the trigger signal is generated.