Abstract: A guidance method and system for an automotive vehicle which switches from an electronic navigational signal method to a dead reckoning method when any of the field strengths of three navigational electromagnetic wave signals drops below a predetermined lower limit or vice versa when the field strengths of the three navigational electromagnetic wave signals all exceed the lower limit. Therefore, even if the navigational wave signals are obstructed by buildings or mountains, it is possible to continuously determine and display the vehicle position. The guidance system according to the present invention comprises a receive-state detection unit for detecting three field strengths and for comparing the detected field strengths with a predetermined lower limit, and a selector for selectively outputting vehicle position signals on the basis of navigational signals or dead reckoning, in addition to the conventional electronic navigation system and dead reckoning system.

Abstract: A self-teaching RCC device robot feedback system including: a robot mechanism; an RCC device carried by the robot mechanism; a robot driver unit for directing motion of the RCC device in an environment; means for determining the displacement of an RCC device with respect to the robot; and an adaptive learning system, responsive to the means for determining displacement, for detecting a pattern of displacements of the RCC device relative to its environment and generating commands to the robot driver unit to direct motion of the RCC device.

Abstract: In a wire matrix printer control system, some characters from a finite alphabet are locally stored as compressed dot matrix objects reflectively symmetric about at least one axis. Upon being referenced and ascertained as a compressed object, the bits are applied to the printhead in column major order up to the axis of symmetry and then applied in reverse column major order. For uncompressed objects, the bits are applied only in column major order.

Abstract: An electronic control system allows control over the safe operation of an aerial work platform machine. The control system uses a firmware programmed digital processor to execute a sequence of steps to monitor and control the safe operation of the work platform machine so that tipping and damage are prevented. The control system has sensors to measure the condition of the work platform machine and has outputs allowing control over the work platform machine.

Abstract: An appliance including a digital programming device for forming a sequence of control signals. When the device is switched on by way of the power supply plug, an unpredictable switch-on phenomenon occurs and the program memory is liable to be addressed in a variety of locations. Therefore, during a preparation routine the start conditions are realized. Furthermore, a multi-bit code is generated and stored in a volatile section of the memory. The operative routine comprises a sub-routine which tests this code. If the code is not correct, the preparation routine has not been followed when the appliance was switched-on. The operative routine is then interrupted and first the preparation routine is executed. All further locations in the non-volatile memory section preferably refer to the preparation routine.

Abstract: In order to provide for substantially reduced costs in acceptance testing of aircraft computers, the acceptance test system described herein includes: a group of input circuits for receiving the computer output data signals; an input circuit adapted to receive signals from the aircraft computer representing the computer input data signals; and a transmitter for transmitting the computer input data to the computer. In this automatic acceptance test system, the computer under test generates both serial and parallel input data signals for itself which are then retransmitted to the computer under test by the automatic test system.

Abstract: An apparatus for controlling the access of a plurality of microprocessors at a data line. The microprocessors are connected by interface components or blocks, logic switching circuits and bus drivers with two lines or conductors. An access request or demand of a processor initiates a signal change at the first line. This signal change causes the transformation of data which is specific to the processor into a delay or a priority signal, upon the occurrence of which there is accomplished a signal change of the second line. As a function thereof there appears at an input of the interface component a signal change which is indicative of the availability of the data line. Upon simultaneous occurrence of access requests or demands of a number of processors the signal change of the second line is brought about by that processor whose priority signal possesses the smallest delay.

Abstract: Sequencer means for a microprogrammed control unit which develops consecutive addresses of microprograms, branches to subroutines with address saving and possible return to microprogram, as well as interrupting microprogram forcings with address saving of the interrupted microprograms.In order to allow the double saving of microprogram and subroutine addresses in case of concurrent interruptions and branches, the sequencer means is provided with two address generation loops each including a register. The two loops have a common portion to which they accede through a multiplexer. The first loop is further coupled to a saving register stack.While the first loop executes the saving of a microprogram address and the latching or a branch address received from the second loop, the second loop executes a first updating and related latching or interrupting microprogram address.

Abstract: A spark timing control system for an uneven firing engine utilizes a microprogrammed engine controller which produces a spark timing control system based on internal calculations using spark advance and dwell variables supplied by a microcomputer. A crankshaft position transducer produces a reference signal having alternate long and short pulses from which the firing cycle may be determined. The microcomputer is interrupted at each falling edge of the reference signal and based on a determination of the existing firing cycle, calculates and supplies appropriate spark advance and dwell numbers to the controller.

Abstract: A control circuit of the present invention comprises a first memory for storing entry words, a second memory for storing a certain number of rule patterns according to which the endings of the entry words may be inflected, and an inflection control device responsive to the first memory and the second memory for inflecting the endings of the words by a particular rule pattern developed from the second memory. In another form of the present invention, an encoder is provided for encoding a word entered into first parts of coded information common to words identified as the same and into second parts of coded information having a difference dependent on the kind of the words. The equivalency between the word entered and one of entry words stored in a memory is determined using only the first parts of coded information.

Abstract: An improved sampling network analyzer is described, in which a stored memory, for example, a programmable read-only memory (PROM), is utilized to store the discrepancies between various predetermined mid-band voltage gains and their desired, exact values, and to supply this correction information to the sampling network analyzer in order to produce a more accurate amplitude measure of the amplitude of voltages applied to the inputs of the sampling network analyzer. In addition, low- and high-frequency characteristic frequencies can be stored, and correction made for the gain-vs-frequency characteristic of an amplifier or amplifier chain. The correction factors are typically measured in final test of the sampling network analyzer, and programmed into a PROM that is incorporated into the particular sampling network analyzer.

Abstract: A digital m of n correlation device using signal and reference shaft registers, modulo 2 adders, unique 1-bit D/A converters, and single resistor analog summing provides a very fast correlation product for pulse compression modulations such as phase or frequency shift keying. The compression ratio for the digital m of n correlation device, according to the present invention, is 168:1 (equal to the number of bits). The device is capable of bit rates in excess of 100 Mbps and is well suited for LSI fabrication.

Abstract: A digital data correlator is provided which detects the presence of a particular sequence, or correlating pattern, of binary data bits in a serial binary data stream, is tolerant of data errors, and is adjustable to accept different numbers of data errors. The correlator includes a shift register of the CMOS type, a plurality of inverters of the CMOS type connected to selected outputs of the register at which bits of a particular logic value are expected for a properly positioned correlating pattern in the register, and a plurality of like-valued resistances coupled to the outputs of the register and to the inverters. Erroneous bits in the register cause an error voltage to be produced at a common node point coupled to the resistances. The value of the error voltage is compared in a comparator against a threshold reference voltage of a value related to an acceptable number of erroneous bits.

Abstract: A microprocessor for facilitating the execution of instructions which require repetitive shift and arithmetic logic unit operations comprises an arithmetic logic unit having a first and a second input and an output, a plurality of registers, at least one of which is a bidirectionally shifting register and multiplexing apparatus for selectively coupling each of said plurality of registers to said first and said second inputs and said output of said arithmetic logic unit.