Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

Abstract: The present disclosure provides a method of forming a crystalline ITO thin film for forming the crystalline ITO thin film on a liquid crystal panel and a method of forming an On-cell type touch panel by using the method of forming a crystalline ITO thin film. The method of forming a crystalline ITO thin film includes: forming a noncrystalline ITO thin film on a surface of a side of a color filter substrate being far away from the liquid crystal layer, by a deposition process; and crystallizing the noncrystalline ITO thin film by an excimer laser anneal process at a preset temperature so as to obtain the crystalline ITO thin film.

Abstract: A semiconductor structure that includes: a substrate, a twin vertical punch-through stopper layer structure connected to the substrate, and a plurality of nanosheets connected to and supported by the twin vertical punch-through stopper structure and isolated from the substrate by an insulating dielectric.

Abstract: A semiconductor device which provides improved reliability. The semiconductor device includes: a wiring substrate having a first surface and a second surface opposite to the first surface; a chip condenser built in the wiring substrate, having a first electrode and a second electrode; a first terminal and a second terminal disposed on the first surface; and a third terminal disposed on the second surface. The semiconductor device further includes: a first conduction path for coupling the first terminal and the third terminal; a second conduction path for coupling the first terminal and the first electrode; a third conduction path for coupling the third terminal and the first electrode; and a fourth conduction path for coupling the second terminal and the first electrode.

Abstract: The present disclosure provides FinFET structures and fabrication methods thereof. An exemplary fabrication method includes providing a substrate having a first region and a second region; forming a first well region in first region and a second well region in the second region; forming at least one first fin in the first region and at least one second fin in the second region; forming a first doped layer covering the first fin; forming a second doped layer covering the second fin; forming first doped sidewall spacers on side surfaces of the first fin and second doped sidewall spacers on side surfaces of the second fin by a mask-less etching process; and performing a thermal annealing process to the first doped sidewall spacers and the second doped sidewall spacers to form a third well region in the first fin and a fourth well region in the second fin, respectively.

Abstract: A fuse structure for dynamic random access memory (DRAM) includes: a shallow trench isolation (STI) in a substrate; a first select gate in the substrate and adjacent to one side of the STI; a second select gate in the substrate and adjacent to another side of the STI; and a gate structure on the STI, the first select gate, and the second select gate.

Abstract: Provided are a lateral p-n junction black phosphorus thin film, and a method of manufacturing the same, and specifically, a lateral p-n junction black phosphorus thin film in which a p-type black phosphorus thin film having a p-type semiconductor property and a n-type black phosphorus thin film having a n-type semiconductor property form a lateral junction by modifying some regions on a surface of the black phosphorus thin film through light irradiation with a compound having a specific chemical structure, and a method of manufacturing the same.

Abstract: A display device (1) includes a substrate (11) having a first surface (S1) and a second surface (S2) that face each other, and having a plurality of light emitting elements (10A) on the first surface, a mounting member (12) disposed to face a portion of the second surface of the substrate, and a base (13) adhered to the second surface of the substrate, and having a depressed portion (13a) that faces the mounting member.

Abstract: A light-emitting device includes a pair of first electrodes arranged separated from and opposing each other on a first surface of a substrate; a light-emitting layer arranged on at least one of the first electrodes; a second electrode arranged on the light-emitting layer; and a bridge layer connecting the first electrodes. The bridge layer is formed of a material having a resistance that falls within a range of 100 k? to 100 M?.

Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer having a first concentration of germanium on a semiconductor substrate, a second semiconductor layer having a second concentration of germanium on the first semiconductor layer, and a third semiconductor layer having a third concentration of germanium on the second semiconductor layer. The method also includes patterning the first, second and third semiconductor layers into at least one fin, and reducing a width of the second semiconductor layer of the at least one fin. In the method, a bottom source/drain region is grown from the substrate adjacent a base portion of the at least one fin, a gate structure is formed on and around the second semiconductor layer, and a top source/drain region is grown from the third semiconductor layer.

Abstract: A solution for packaging an optoelectronic device by aligning an optical element with respect to the package is provided. After initial placement of the optical element on the device package, an emitted light pattern can be measured and compared to a target light pattern. Subsequently, the position of the optical element can be adjusted. The emitted light pattern can be repeatedly compared to the target light pattern until the emitted light pattern is within an acceptable range of error and the optical element can be secured to the device package.

Abstract: There is improved performance of a semiconductor device including a fin-type low-withstand-voltage transistor and a fin-type high-withstand-voltage transistor. A low-withstand-voltage transistor is formed on each of a plurality of first fins isolated from each other by a first element isolation film, and a high-withstand-voltage transistor, which has a channel region including tops and side surfaces of a plurality of second fins and a top of a semiconductor substrate between the second fins adjacent to each other, is formed. At this time, a top of a second element isolation film surrounding the second fins including part of the channel region of one high-withstand-voltage transistor is lower than a top of the first element isolation film.

Abstract: A semiconductor device includes an active region formed over a substrate. The active region includes a FET and a diode. The FET includes one or more FET fingers. Each FET finger includes a FET source region, a FET drain region, and a lateral FET gate electrode. The diode includes one or more diode fingers. Each of the diode fingers includes a diode anode region electrically coupled to the FET source region, a diode cathode region electrically coupled to the FET drain region, and a lateral diode gate electrode electrically coupled to the diode anode region and electrically isolated from the lateral FET gate electrode. The FET fingers are active fingers of the semiconductor device and the diode fingers are dummy fingers of the semiconductor device. The diode is configured to clamp a maximum voltage developed across the FET drain region and the FET source region.

Abstract: A microelectronic device includes a reflow structure. The reflow structure has a copper-containing member and a solder member, and a barrier layer between them. The barrier layer has metal grains, with a diffusion barrier filler between the metal grains. The metal grains include at least a first metal and a second metal, each selected from nickel, cobalt, lanthanum, and cerium, with each having a concentration in the metal grains of at least 10 weight percent. The diffusion barrier filler includes at least a third metal, selected from tungsten and molybdenum. A combined concentration of tungsten and molybdenum in the diffusion barrier filler is higher than in the metal grains to provide a desired resistance to diffusion of copper. The barrier layer includes 2 weight percent to 15 weight percent of the combined concentration of tungsten, and molybdenum. A bump bond structure and a lead frame package are disclosed.

Abstract: A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.

Abstract: An assembly can include solid-state overvoltage firing switch operable to control an explosive device. The solid-state overvoltage firing switch can include a substrate layer. The solid-state overvoltage firing switch can also include a conductive anode and a conductive cathode positioned on the substrate layer. A gap can physically separate the conductive anode from the conductive cathode. The conductive anode can be operable to receive a voltage from a power source. The solid-state overvoltage firing switch can further include an insulator layer adjacent to the conductive anode and the conductive cathode. At least part of the insulator layer can fill the gap. The insulator layer can cover a first portion of the conductive anode and a second portion of the conductive cathode.

Abstract: Some embodiments include an apparatus having a well region extending into a semiconductor substrate. A first conductive element is over the well region, and a second conductive element is over the first conductive element. A hole extends through the first conductive element. A connecting element extends from the second conductive element to the well region, and passes through the hole.

Abstract: A color conversion composition includes the following Component (A) and Component (B): Component (A): an organic light-emitting material; and Component (B): at least one of a polyester resin having a partial structure represented by General Formula (1) in its molecular structure of the polyester resin and a resin containing a bisphenol structure represented by General Formula (2): where Y is a divalent saturated aliphatic hydrocarbon group having at least one of a tertiary carbon and a quaternary carbon, where R1 and R2 each represent hydrogen or a C1-20 organic group; R1 and R2 may be the same as or different from each other.

Abstract: A semiconductor device that outputs a radio-frequency (RF) signal with high power is disclosed. The semiconductor device includes a housing, a semiconductor chip, an impedance converter, a capacitor, and a bonding wire. The housing includes a heat sink, an output lead terminal, and a bias terminal electrically isolated from the output lead terminal. The semiconductor chip is mounted on the heat sink of the housing. The impedance converter provides an input port, an output port, and an intermediate port between the input port and the output port thereof. The capacitor is mounted on the heat sink and between the impedance converter and the output lead terminal. The bonding wire connects the bias lead terminal with the intermediate port.

Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.