Apparatuses having an interconnect extending from an upper conductive structure, through a hole in another conductive structure, and to an underlying structure

- Micron Technology, Inc.

Some embodiments include an apparatus having a well region extending into a semiconductor substrate. A first conductive element is over the well region, and a second conductive element is over the first conductive element. A hole extends through the first conductive element. A connecting element extends from the second conductive element to the well region, and passes through the hole.

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Description
TECHNICAL FIELD

Apparatuses having an interconnect extending from an upper conductive structure, through a hole in another conductive structure, and to an underlying structure. CMOS configurations having bias voltage connections extending from upper conductive levels, through one or more conductive elements, and to a diffusion region associated with an underlying semiconductor substrate.

BACKGROUND

Integrated arrangements may include multiple conductive levels over a semiconductor substrate. The conductive levels may be vertically stacked relative to one another such that some conductive levels are under other conductive levels. The conductive levels may comprise wiring or other conductive structures. It may be desired to form an interconnect which extends from a conductive structure of an upper conductive level, through one or more of the lower conductive levels, and to an underlying structure (for instance, a diffusion region associated with the semiconductor substrate). It can be difficult to form such interconnects. If the interconnects serpentine around conductive wiring within the lower conductive levels, the interconnects will be long and will have higher resistance (i.e., increased IR drop) than would shorter interconnects. If instead the interconnects are formed to directly pass through underlying conductive levels, the interconnects will advantageously be short and have desired low resistance. However, the wiring within the underlying conductive levels may end up serpentining around the interconnects and accordingly will be lengthened and have higher resistance than if the wiring were shorter.

It would be desirable to develop new integrated arrangements in which interconnects extend from a conductive structure of an upper conductive level, through one or more lower conductive levels, and to an underlying structure; while avoiding the problems discussed above.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic top view of a fragment of an example construction.

FIG. 2 is a diagrammatic top view of the fragment of FIG. 1, illustrating an example arrangement of circuitry.

FIGS. 2A, 2B and 2C are diagrammatic cross-sectional side views along the lines A-A, B-B and C-C of FIG. 2, respectively.

FIG. 3 is a diagrammatic schematic illustration of an example CMOS configuration.

FIG. 4 is a diagrammatic cross-sectional side view of an example CMOS configuration.

 DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Some embodiments include integrated arrangements having multiple conductive levels over a semiconductor substrate. At least one interconnect extends downwardly from at least one conductive structure associated with an upper conductive level, and couples the conductive structure of the upper conductive level to a structure under the upper conductive level (for instance, to a diffusion region associated with the semiconductor substrate). The interconnect passes through at least one intermediate conductive level which is between the substrate and the upper conductive level; and specifically passes through a hole in a conductive element (e.g., wire) which is associated with the intermediate conductive level. Although conductive elements having holes extending therethrough may have increased resistance as compared to analogous conductive elements lacking such holes, in general it is found that the overall resistance associated with integrated arrangements of the example embodiments described herein is better (i.e., lower) as compared to conventional arrangements (e.g., the conventional arrangements discussed above in the “Background” section of this disclosure).

The arrangements of the example embodiments described herein may be utilized in any suitable applications. For instance, the arrangements may be utilized in CMOS applications. Example embodiments are described with reference to FIGS. 1-4.

Referring to FIG. 1, a construction 10 is shown to comprise n-well regions 12 alternating with p-well regions 14. Intervening regions 15 are shown to be between the n-well regions 12 and the p-well regions 14. The n-well regions 12 are shown to be spaced from the p-well regions 14 in order to clearly show the regions 12 and 14 in the top view of FIG. 1. In practice, the n-well regions 12 may be directly against the p-well regions 14.

The n-well regions 12 and the p-well regions 14 are doped diffusion regions extending into a semiconductor substrate 16. The semiconductor substrate 16 comprises semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the semiconductor substrate 16 may include one or more materials associated with integrated circuit fabrication. Example materials which may be included within the semiconductor substrate 16, are refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

One of the n-well regions 12 is labeled as region 12a, and one of the p-well regions 14 is labeled as region 14a. The region 12a is substantially identical to the other n-well regions 12, and is called out as region 12a only to enable such region to be specifically identified. Similarly, the region 14a is substantially identical to all other p-well regions 14, and is called out as region 14a only to enable such region to be specifically identified. The term “substantially identical” means identical to within reasonable tolerances of fabrication and measurement.

The n-well region 12a is an immediate neighbor of the p-well region 14a. In some embodiments, the n-well region 12a may be directly adjacent to the immediately neighboring p-well region 14a; and in other embodiments may be spaced from the immediately neighboring p-well region 14a by one or more intervening insulative materials. The term “directly adjacent” means that the n-well region 12a directly contacts the p-well region 14a, rather than being spaced from the p-well region 14a by one or more intervening materials.

PMOS (p-channel metal-oxide semiconductor) transistors may be formed across the n-well regions 12, and NMOS (n-channel metal-oxide semiconductor) transistors may be formed across the p-well regions 14. The PMOS transistors and NMOS transistors may be incorporated into CMOS (complementary metal-oxide semiconductor) devices, with example CMOS configurations being described below with reference to FIGS. 3 and 4.

Referring still to FIG. 1, CMOS regions A, B, C, and D are shown to each comprise a portion of one of the n-well regions 12 together with a neighboring portion of one of the p-well regions 14.

It can be desired to provide n-well bias voltage (VNW) to the n-well regions 12, and to provide p-well bias voltage (VPW) to the p-well regions 14. The VNW and VPW may be utilized to prevent latch-up relative to CMOS, and/or for other purposes. In the illustrated embodiment, the VNW is coupled with circuitry 18 and the VPW is coupled with circuitry 20. The circuitries 18 and 20 are configured to provide appropriate voltages.

The illustrated fragment of construction 10 comprises five of the alternating n-well and p-well regions 12 and 14. Any suitable number of alternating n-well and p-well regions may be utilized across the construction 10.

The alternating n-well and p-well regions 12 and 14 may be utilized for any suitable application(s). For instance, in some applications the alternating regions may be incorporated into CMOS and utilized as part of a logic circuit.

Referring to FIGS. 2, 2A, 2B and 2C, example circuitry is shown provided across the CMOS regions A-D as part of the construction (i.e., assembly, apparatus, structure, architecture, etc.) 10. As a preliminary matter, it is noted that the n-well regions 12 appear to be spaced from the p-well regions 14 by intervening regions 15 in the top view of FIG. 2, but the regions 12 and 14 are directly adjacent to one another in the cross-sectional side views of FIGS. 2A-C. The intervening regions 15 are provided relative to the top view of FIG. 2 in order to enable the regions 12 and 14 to be clearly distinguished from one another. The cross-sectional side views of FIGS. 2A-C more accurately reflect the example embodiment intended to be conveyed by FIGS. 2, 2A, 2B and 2C. However, it should be noted that the invention also includes embodiments in which a p-well region is spaced from a neighboring n-well region by one or more insulative materials; and FIG. 2 may be considered to convey such aspects of the invention.

The circuitry of FIGS. 2, 2A, 2B and 2C includes three vertically-stacked conductive levels which are shown in the cross-sectional side views of FIGS. 2A-C as “Metal 0”, “Metal 1” and “Metal 2”. Each conductive level comprises conductive elements (i.e., conductive structures; such as, for example, wiring), as discussed in more detail below. Although the conductive levels are indicated to be “metal” levels, it is to be understood that the conductive elements within the conductive levels may comprise any suitable conductive materials. For instance, the conductive elements may comprise one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). Thus, although the conductive levels are labeled as “metal” levels, it is to be understood that the conductive levels may include conductive elements which comprise, consist essentially of, or consist of conductively-doped semiconductor material.

The p-well region 14a as illustrated as an example of the p-well regions 14 in the cross-sectional views of FIGS. 2A-C, and the n-well region 12a is illustrated as an example of the n-well regions 12. The p-well region 14a and the n-well region 12a are supported over a deep n-well 25 in the illustrated embodiment.

The cross-sectional views of FIGS. 2A-C show an n-type diffusion region 22 (i.e., an n-type transistor region) extending into the p-well region 14a, and show a p-type diffusion region 24 (i.e., a p-type transistor region) extending into the n-well region 12a. In some embodiments, the regions 22 and 24 may be referred to as diffusion regions which are of opposite type conductivity relative to the wells under the diffusion regions (with p-type and n-type being understood to be of opposite conductivity type relative to one another).

FIGS. 2A-C show that a heavily-doped p-type region 26 extends into the p-well region 14a, and that a heavily-doped n-type region 28 extends into the n-well region 12a.

Circuit elements 30 are diagrammatically illustrated as being associated with the n-type diffusion region 22, and circuit elements 32 are diagrammatically illustrated as being associated with the p-type diffusion region 24. The circuit elements 30 may be understood to be generically representative of circuit elements associated with NMOS transistors (with example NMOS transistors being described below with reference to FIGS. 3 and 4), and the circuit elements 32 may be understood to be generically representative of circuit elements associated with PMOS transistors (with example PMOS transistors being described below with reference to FIGS. 3 and 4).

The first conductive level (the level indicated as “Metal 0” in the cross-sectional views of FIGS. 2A-C) is over the circuit elements 30 and 32. The first conductive level is shown in the cross-sectional views of FIGS. 2A-C to have a first conductive element (i.e., first circuit element) 34 over the p-well region 14a, and to have a second conductive element (i.e., second circuit element) 36 over the n-well region 12a. The first conductive element 34 is electrically coupled with the NMOS circuit elements 30, and the second conductive element 36 is electrically coupled with the PMOS circuit elements 32.

The second conductive level (the level indicated as “Metal 1” in the cross-sectional views of FIGS. 2A-C) comprises the voltage supply lines Vss and Vdd. The voltage supply line Vss may be referred to as a third conductive element (or third circuit element) 38, and the voltage supply line Vdd may be referred to as a fourth conductive element (or fourth circuit element) 40.

The third conductive level (the level indicated as “Metal 2” in the cross-sectional views of FIGS. 2A-C) comprises a fifth conductive element (i.e., fifth circuit element) 42 supplying the p-well bias voltage (VPW), and a sixth conductive element (i.e., sixth circuit element) 44 supplying the n-well bias voltage (VNW).

The levels Metal 0, Metal 1 and Metal 2 are referred to as first, second and third conductive levels, respectively, in the description above. In alternative descriptions, the levels may be identified with different descriptors. For instance, Metal 1 may be referred to as the third level and Metal 2 may be referred to as the second level. FIGS. 2A-2C provide descriptors L1, L3 and L2 adjacent conductive levels Metal 0, Metal 2 and Metal 1, respectively, to specifically indicate an arrangement in which the levels are described as a first conductive level, third conductive level and second conductive level, respectively. In some embodiments, either of the conductive levels Metal 0 and Metal 1 may be considered to be a first conductive level, and the conductive level Metal 2 may be considered to be a second conductive level which is over the first conductive level.

There may be additional conductive levels besides the three conductive levels of FIGS. 2, 2A, 2B and 2C in some embodiments; and there may be only two conductive levels in other embodiments.

A first opening 50 extends through Vss supply line 38 (i.e., conductive element 38), and through the conductive element 34 of level Metal 0, over p-well region 14a. A second opening 52 extends through Vdd supply line 40 (i.e., conductive element 40), and through the conductive element 36 of level Metal 0, over n-well region 12a. The first opening 50 may be considered to comprise a first hole 54 passing through the conductive element 34, and to comprise a second hole 56 passing through the conductive element 38 (with the holes 54 and 56 being shown in FIGS. 2A and 2B). The second opening 52 may be considered to comprise a first hole 58 passing through the conductive element 36, and to comprise a second hole 60 passing through the conductive element 40 (with the holes 58 and 60 being shown in FIGS. 2A and 2B).

In some embodiments, the holes 54 and 58 in openings 50 and 52 may be referred to as first and second holes respectively; and the conductive elements 34 and 36 may be referred to as first and second conductive elements having the holes 54 and 58 passing therethrough.

In some embodiments, the holes 56 and 60 in openings 50 and 52 may be referred to as first and second holes respectively; and the conductive elements 38 and 40 may be referred to as first and second conductive elements having the holes 56 and 60 passing therethrough.

In some embodiments, one of the holes 54 and 58 may be referred to as a first hole, and the other may be referred to as an additional hole. In such embodiments, one of the conductive elements 38 and 40 may be referred to as a first conductive element elevationally above the holes 54 and 58, and the other may be referred to as an additional conductive element elevationally above the holes 54 and 58. In such embodiments, one of the conductive elements 42 and 44 (the VPW and VNW elements) may be referred to as a second conductive element and the other may be referred to as a third conductive element.

In some embodiments, one of the holes 56 and 60 may be referred to as a first hole, and the other may be referred to as an additional hole. In such embodiments, one of the conductive elements 34 and 36 may be referred to as a first conductive element elevationally below the holes 56 and 60, and the other may be referred to as an additional conductive element elevationally below the holes 56 and 60. In such embodiments, one of the conductive elements 42 and 44 (the VPW and VNW elements) may be referred to as a second conductive element and the other may be referred to as a third conductive element.

In some embodiments, the conductive elements 34 and 42 of FIG. 2A may be referred to as first and second conductive elements, respectively; and the conductive element 38 (Vss element) may be referred to as a third conductive element which is elevationally between the first and second conductive elements.

In some embodiments, the conductive elements 36 and 44 of FIG. 2B may be referred to as first and second conductive elements, respectively; and the conductive element 40 (Vdd element) may be referred to as a third conductive element which is elevationally between the first and second conductive elements.

A connecting element (i.e., interconnect) 62 extends from the conductive element 42 (VPW) to the p-type diffusion region 26 associated with the p-well region 14a, as shown in FIG. 2A. Also, a connecting element (i.e., interconnect) 64 extends from the conductive element 44 (VNW) to the n-type diffusion region 28 associated with the n-well region 12a, as shown in FIG. 2B. The connecting element 62 may be considered to extend through the opening 50 to couple the p-well bias voltage (VPW) with the p-well region 14a. Similarly, the connecting element 64 may be considered to extend through the opening 52 to couple the n-well bias voltage (VNW) with the n-well region 12a.

In some embodiments, one of the holes 54 and 56 associated with the first opening 50 may be considered to be a first hole; and one of the holes 58 and 60 associated with the second opening 52 may be considered to be a second hole. The connecting element 62 may be considered to be a first connecting element which extends through the first hole to couple the conductive element 42 (VPW) with the p-well region 14a, and the connecting element 64 may be considered to be a second connecting element which extends through the second hole to couple the conductive element 44 (VNW) with the n-well region 12a. Alternatively, one of the holes 58 and 60 may be considered to be the first hole, one of the holes 54 and 56 may be considered to be the second hole, the connecting element 64 may be considered to be the first connecting element, and the connecting element 62 may be considered to be the second connecting element.

In some embodiments, one of the holes 54 and 56 associated with the opening 50 may be considered to be a first hole; and one of the holes 58 and 60 associated with the opening 52 may be considered to be an additional hole. The connecting element 62 may be considered to be a first connecting element, and the connecting element 64 may be considered to be an additional connecting element.

In some embodiments, one of the holes 58 and 60 associated with the opening 52 may be considered to be a first hole; and one of the holes 54 and 56 associated with the opening 50 may be considered to be an additional hole. The connecting element 64 may be considered to be a first connecting element, and the connecting element 62 may be considered to be an additional connecting element.

In some embodiments, the hole 54 of opening 50 may be considered to be a first hole, and the hole 56 of the opening 50 may be considered to be an additional hole. The connecting element 62 may be considered to pass through both the first hole and the additional hole.

In some embodiments, the hole 58 of opening 52 may be considered to be a first hole, and the hole 60 of the opening 52 may be considered to be an additional hole. The connecting element 64 may be considered to pass through both the first hole and the additional hole.

Notably, FIG. 2B shows that a lower portion of connecting element 62 is present under the conductive element 44 (VNW), but is not coupled with the conductive element 44; and FIG. 2A shows that a lower portion of connecting element 64 is present under the conductive element 42 (VPW), but is not coupled with the conductive element 42.

In the illustrated embodiment of FIGS. 2A-C, additional connecting elements 66 couple the conductive element 38 (Vss) with the conductive element 34; and additional connecting elements 68 couple the conductive element 40 (Vdd) with the conductive element 36.

The top view of FIG. 2 shows that the conductive element 38 (Vss) is configured as a wiring extending primarily along a first direction represented by an axis 5, and that the conductive element 40 (Vdd) is also configured as a wiring extending primarily along the first direction represented by the axis 5. A wiring is described as extending “primarily” along a direction to indicate that the wiring may or may not be straight, but the overall general direction of the wiring is along the stated direction (i.e., the wiring elongates along the stated direction). The top view of FIG. 2 also shows that the p-well bias voltage (VPW) conductive element 42 is configured as a wiring extending primarily along a second direction represented by an axis 7, and that the n-well bias voltage (VNW) conductive element 44 is also configured as a wiring extending primarily along the second direction represented by the axis 7.

The second direction of the axis 7 crosses the first direction of the axis 5, and in the illustrated embodiment is substantially orthogonal to the first direction of the axis 5 (with the term “substantially orthogonal” meaning orthogonal to within reasonable tolerances of fabrication and measurement).

Insulative materials (not shown) would generally be provided between the various conductive elements and interconnects of FIGS. 2, 2A, 2B and 2C, as will be recognized by persons of ordinary skill in the art. The insulative materials are not shown in order to simplify the drawings. The insulative materials may comprise any suitable compositions or combinations of compositions; including, for example, silicon dioxide, silicon nitride, various high-k materials (where high-k means a dielectric constant greater than that of silicon dioxide), etc.

The top view of FIG. 2 shows the connecting elements 62 and 64 configured as pedestals 63 and 65, respectively; with the pedestals 63 and 65 extending downwardly through the openings 50 and 52. In the shown embodiment, the openings 50 and 52 have a rectangular shape (i.e., a rectangular inner periphery), and the pedestals 63 and 65 have rectangular shapes (i.e., rectangular outer peripheries) which nest within the rectangular-shaped openings. Annular insulative regions 66 laterally surround the pedestals 63 and 65. The insulative regions 66 are shown as voids in FIG. 2. In practice, the insulative regions 66 may be filled with any suitable insulative material; such as, for example, one or more of silicon dioxide, silicon nitride, high-k dielectric material, etc.

The annular insulative regions 66 may be considered to be “donut-shaped,” in that they are configured as rings.

Although the openings 50 and 52 are shown to be rectangular-shaped in the illustrated embodiment, it is to be understood that the openings may have any suitable shape; such as, for example, round, elliptical, polygonal, etc. The pedestals 63 and 65 may be configured to have shapes complementary to the shapes of the openings so that they nest within the openings analogous to the nested configuration shown in FIG. 2. Alternatively, the pedestals 63 and 65 may have shapes which are not complementary to the internal peripheries of the openings 50 and 52. For instance, in some embodiments the openings may be square (or other polygonal) and the pedestals may be round (e.g., circular or elliptical). As another example, the openings may be round, and the pedestals may be square (or other polygonal).

Plugs 70 are diagrammatically illustrated in the top view of FIG. 2 (and example plugs 70 are shown in the cross-sectional side views of FIGS. 2B and 2C). The plugs 70 are shown in dashed-line view in FIG. 2 in order to differentiate the plugs 70 from the remainder of the pedestals 63 and 65. The plugs 70 connect the pedestals 63 and 65 with an appropriate bias voltage (VPW or VNW). In the shown embodiment, the pedestal 63 is connected with VPW, and the pedestal 65 is connected with VNW.

An advantage of forming the openings 50 and 52 through the conductive elements 34, 36, 38 and 40 (as shown in FIGS. 2, 2A, 2B and 2C) is that the bias voltages (VPW and VNW) may be coupled from the upper level (i.e., the Metal 2 level) to the underlying substrate 16 with reasonable resistance being maintained along all of the conductive levels (i.e., the levels identified as Metal 1, Metal 0 and Metal 2), and along the interconnects 62 and 64. The interconnects 62 and 64 do not serpentine around wiring associated with the lower levels (Metal 0 and Metal 1), and the resistance along the wiring of the lower levels is not substantially altered to accommodate the interconnects 62 and 64. Accordingly, the overall resistance across the various conductive elements and connecting elements of the configuration of FIGS. 2, 2A, 2B and 2C may be kept low as compared to analogous configurations utilizing conventional architectures. Such may advantageously lead to improved performance of configurations of the present invention as compared to conventional configurations. For instance, configurations of the present invention may require less power than conventional configurations, may have improved lifetimes as compared to conventional configurations, may have enhanced speed as compared to conventional configurations, etc.

The illustrated conductive elements (wirings) of FIGS. 2, 2A, 2B and 2C are examples of some of the wirings which may be associated with example embodiment architectures. Persons of ordinary skill in the art will recognize that there may also be additional wirings, such as, for example, wirings for input signals, wirings for output signals, etc.

The configuration of FIGS. 2, 2A, 2B and 2C may be utilized for CMOS; such as, for example, CMOS of logic circuitry. Example CMOS architecture is described with reference to FIGS. 3 and 4.

Referring to FIG. 3, an example configuration of CMOS 80 is illustrated with a schematic diagram. The CMOS 80 comprises a PMOS transistor 82 having a first source/drain region 81, a second source/region 83, and a gate 85. The CMOS 80 also comprises an NMOS transistor 84 having a source/drain 91 coupled to the source/drain region 83, having another source/drain region 87, and having a gate 89. The source/drain region 81 of the PMOS transistor 82 is coupled with a Vdd supply 40, and the source/drain region 87 of the NMOS transistor is coupled with a Vss supply 38. The gates 85 and 89 of the transistors 82 and 84 are coupled with an input “I”, and the shared source/drain region 83 is coupled with an output “O”.

The example CMOS 80 is diagrammatically illustrated in FIG. 4 along a cross-sectional view. The conductive levels Metal 0, Metal 1 and Metal 2 are shown in FIG. 4. The NMOS gate 89 is labeled as a gate G1, and the PMOS gate 85 is labeled as a gate G2. The NMOS source/drain regions 84 and 91 are part of the n-type diffusion region 22, and the PMOS source/drain regions 81 and 83 are part of the p-type diffusion region 24.

The source/drain regions 83 and 91 of the CMOS configuration 80 are shown to be coupled with the conductive element 34 along the conductive level of Metal 0, with such conductive element being tied to the output “O”. The source/drain regions 84 and 81 of the CMOS configuration 80 extend to supply lines 38 (Vss) and 40 (Vdd); with the supply lines 38 and 40 including wiring which extends along the conductive level Metal 1. Also, the CMOS configuration 80 is shown to comprise the diffusion regions 26 and 28, which are coupled with bias voltages (VPW) and (VNW); with the bias voltage VPW being supplied by wiring 42 which extends along the conductive level of Metal 2, and with the bias voltage VNW being supplied by wiring 44 which extends along the conductive level of Metal 2.

The NMOS gate 89 and the PMOS gate 85 are coupled with a conductive element 100, which in turn is coupled with the input “I”. The conductive element 100 is shown with a dashed line to indicate that it may be in any suitable location. For instance, the conductive element 100 may extend along one of the illustrated conductive levels Metal 0, Metal 1 or Metal 2; may extend along a level between two of the illustrated conductive levels; may extend along a level beneath the level of Metal 0; may extend along a level above the level of Metal 2; etc.

The assemblies and structures discussed above may be utilized within integrated circuits (with the term “integrated circuit” meaning an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

The terms “dielectric” and “insulative” may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term “dielectric” in some instances, and the term “insulative” (or “electrically insulative”) in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The descriptions provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections, unless indicated otherwise, in order to simplify the drawings.

When a structure is referred to above as being “on” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on” or “directly against” another structure, there are no intervening structures present.

Structures (e.g., layers, materials, etc.) may be referred to as “extending vertically” to indicate that the structures generally extend upwardly from an underlying base (e.g., substrate). The vertically-extending structures may extend substantially orthogonally relative to an upper surface of the base, or not.

Some embodiments include an apparatus having a well region extending into a semiconductor substrate. A first conductive element is over the well region and a second conductive element is over the first conductive element. A hole extends through the first conductive element. A connecting element extends from the second conductive element to the well region, and passes through the hole.

Some embodiments include an apparatus having a pair of well regions extending into a semiconductor substrate. One of the well regions is a p-well region, and the other of the well regions is an n-well region. A first conductive level is over the p-well region and is over the n-well region. The first conductive level includes a first conductive element directly over the p-well region, and includes a second conductive element directly over the n-well region. A second conductive level is over the first conductive level. The second conductive level includes a p-well bias voltage and an n-well bias voltage. A first hole passes through the first conductive element. A second hole passes through the second conductive element. A first interconnect extends through the first hole and couples the p-well bias voltage with the p-well region. A second interconnect extends through the second hole and couples the n-well bias voltage with the n-well region.

Some embodiments include an apparatus having a pair of well regions extending into a semiconductor substrate. One of the well regions is a p-well region, and the other of the well regions is an n-well region. An n-type diffusion region is over the p-well region. A p-type diffusion region is over the n-well region. A first conductive level is over the p-well region and is over the n-well region. The first conductive level includes a first conductive element coupled with NMOS transistors associated with the n-type diffusion region, and includes a second conductive element coupled with PMOS transistors associated with the p-type diffusion region. A second conductive level is over the first conductive level. The second conductive level includes a p-well bias voltage and an n-well bias voltage. A first hole passes through the first conductive element. A second hole passes through the second conductive element. A first interconnect extends through the first hole and couples the p-well bias voltage with the p-well region. A second interconnect extends through the second hole and couples the n-well bias voltage with the n-well region.

In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An apparatus comprising:

a semiconductor substrate;
a well region extending into the semiconductor substrate;
a first conductive element over the well region;
a second conductive element over the first conductive element;
a hole extending through the first conductive element;
a connecting element extending from the second conductive element to the well region, and passing through the hole;
wherein the first conductive element is within a first conductive level, wherein the hole is a first hole extending through the first conductive level, wherein the well region is a first well region under the first conductive level; and further comprising: a second well region under the first conductive level and having an opposite conductivity-type relative to the first well region; a third conductive element over the first conductive level; an additional hole extending through an additional conductive element within the first conductive level; and an additional connecting element coupled between the third conductive element and the second well region, and passing through the additional hole.

2. An apparatus comprising:

a semiconductor substrate;
a pair of well regions extending into the semiconductor substrate; one of the well regions being a p-well region, and the other of the well regions being an n-well region;
a first conductive level over the p-well region and over the n-well region; the first conductive level comprising a first conductive element directly over the p-well region, and comprising a second conductive element directly over the n-well region;
a second conductive level over the first conductive level; the second conductive level comprising a p-well bias voltage and an n-well bias voltage;
a first hole passing through the first conductive element;
a second hole passing through the second conductive element;
a first interconnect extending through the first hole and coupling the p-well bias voltage with the p-well region;
a second interconnect extending through the second hole and coupling the n-well bias voltage with the n-well region; and
wherein the p-well region is directly adjacent to the n-well region.

3. An apparatus comprising:

a semiconductor substrate;
a pair of well regions extending into the semiconductor substrate; one of the well regions being a p-well region, and the other of the well regions being an n-well region;
a first conductive level over the p-well region and over the n-well region; the first conductive level comprising a first conductive element directly over the p-well region, and comprising a second conductive element directly over the n-well region;
a second conductive level over the first conductive level; the second conductive level comprising a p-well bias voltage and an n-well bias voltage;
a first hole passing through the first conductive element;
a second hole passing through the second conductive element;
a first interconnect extending through the first hole and coupling the p-well bias voltage with the p-well region;
a second interconnect extending through the second hole and coupling the n-well bias voltage with the n-well region; and
wherein the first conductive element is coupled with Vss, and wherein the second conductive element is coupled with Vdd.

4. The apparatus of claim 3, wherein the p-well bias voltage comprises a first wiring; wherein the n-well bias voltage comprises a second wiring; wherein the first and second conductive elements extend primarily along a first direction, and wherein the first and second wirings extend primarily along a second direction which crosses the first direction.

5. The apparatus of claim 4, wherein the second direction is substantially orthogonal to the first direction.

6. An apparatus comprising:

a semiconductor substrate;
a pair of well regions extending into the semiconductor substrate; one of the well regions being a p-well region, and the other of the well regions being an n-well region;
a first conductive level over the p-well region and over the n-well region; the first conductive level comprising a first conductive element directly over the p-well region, and comprising a second conductive element directly over the n-well region;
a second conductive level over the first conductive level; the second conductive level comprising a p-well bias voltage and an n-well bias voltage;
a first hole passing through the first conductive element;
a second hole passing through the second conductive element;
a first interconnect extending through the first hole and coupling the p-well bias voltage with the p-well region;
a second interconnect extending through the second hole and coupling the n-well bias voltage with the n-well region;
an n-type diffusion region over the p-well region;
a p-type diffusion region over the n-well region;
wherein the first conductive element is coupled with NMOS transistors associated with the n-type diffusion region; and
wherein the second conductive element is coupled with PMOS transistors associated with the p-type diffusion region.

7. The apparatus of claim 6, wherein the first and second conductive elements are within a CMOS configuration.

8. An apparatus comprising:

a semiconductor substrate;
a pair of well regions extending into the semiconductor substrate; one of the well regions being a p-well region, and the other of the well regions being an n-well region;
an n-type diffusion region over the p-well region;
a p-type diffusion region over the n-well region;
a first conductive level over the p-well region and over the n-well region; the first conductive level comprising a first conductive element coupled with NMOS transistors associated with the n-type diffusion region, and comprising a second conductive element coupled with PMOS transistors associated with the p-type diffusion region;
a second conductive level over the first conductive level; the second conductive level comprising a p-well bias voltage and an n-well bias voltage;
a first hole passing through the first conductive element;
a second hole passing through the second conductive element;
a first interconnect extending through the first hole and coupling the p-well bias voltage with the p-well region; and
a second interconnect extending through the second hole and coupling the n-well bias voltage with the n-well region.

9. The apparatus of claim 8, wherein the first and second conductive elements are within a CMOS configuration.

10. The apparatus of claim 8, wherein the p-well region is directly adjacent to the n-well region.

11. The apparatus of claim 8, further comprising a third conductive level between the first and second conductive levels; the third conductive level comprising a third conductive element directly over the p-well region, and comprising a fourth conductive element directly over the n-well region; and wherein:

the first hole passes through the third conductive element; and
the second hole passes through the fourth conductive element.

12. The apparatus of claim 11, wherein the third conductive element is coupled with Vss, and wherein the fourth conductive element is coupled with Vdd.

Referenced Cited
U.S. Patent Documents
5760429 June 2, 1998 Yano
6583001 June 24, 2003 Burr
6861752 March 1, 2005 Kajiyama
Patent History
Patent number: 10410934
Type: Grant
Filed: Dec 7, 2017
Date of Patent: Sep 10, 2019
Patent Publication Number: 20190181053
Assignee: Micron Technology, Inc. (Boise, ID)
Inventors: Nanae Yokoyama (Kanagawa), Ryota Suzuki (Kanagawa), Makoto Sato (Kanagawa)
Primary Examiner: Roy K Potter
Application Number: 15/835,210
Classifications
Current U.S. Class: Multi-level Metallization (257/211)
International Classification: H01L 21/768 (20060101); H01L 21/8238 (20060101); H01L 23/528 (20060101);