Abstract: An adaptive filter system has a first and a second filter subsystem of like construction, each having a series of delay elements for imparting a unit delay of one sampling interval to successive input samples in order to concurrently obtain a set of input samples of different sampling times. Each set of input samples are multiplied by respective coefficients, and the resulting values are added together for comparison with a reference signal. The coefficients are updated for each new set of input samples. For such updating, the first subsystem uses the step gain that is fixed at one, whereas the step gain used by the second subsystem is varied with time for faster convergence and smaller convergence error.

Abstract: A method and apparatus for approximating a sigmoidal response using digital circuitry for neural network computations. The digital circuitry in processing element (16) produces the neuron output signal (110) by performing a squashing operation which determines an approximation of a sigmoid function. In one form, the present invention uses digital circuitry (16) in data processor (10) to approximate a sigmoid function of a neuron (100) using a plurality of parabolas. In an alternate embodiment, the sigmoid function of neuron (100) is approximated using a quasi-log.sub.2 function.

Abstract: A rank order filter is disclosed in which the maximum value, the minimum value and the median value are determined in a 3.times.3 local area having three sample values in each of column and row. The three sample values in the 3.times.3 local area are rearranged in descending order of magnitude by column, and the maximum values or the minimum values in each column are compared with each other thereby to determine the maximum value or the minimum value in the 3.times.3 local area. Also, after comparing the median values with each other in each column, the maximum value in the column having the minimum median value, the minimum value in the column having the maximum median value and the median value in the column having the median median value are compared with each other. The result of comparison is used to determine the median value in the 3.times.3 local area.

Abstract: The present invention is directed toward an combined decoder/adder circuit which provides faster access to a cache in a microprocessor than implementations which include an adder circuit which is followed by a decoder circuit. By decoding the upper order bits of a first operand and then rotating the upper order bits of the first operand by the upper order bits of a second operand, followed by an additional shift by one which is enabled by a carry generator the overall speed of the critical path is greatly increased. Accordingly, the time needed for generating an effective address (EA) and therefore accessing the cache is significantly decreased. The present invention has significant utility in microprocessors in which the word line decode is the critical path.

Abstract: An automated storage system transports data cartridges between a storage device and a plurality of storage cells via a picker assembly. The storage cells are formed of one or more removable magazines. The picker assembly accurately locates each data cartridge within a storage cell by first establishing a zero position reference and locating a home position relatively therefrom. The home position is a predetermined point on each magazine. An infrared detector and infrared sensor are situated on the picker assembly for precisely locating the home position. Each cartridge is known to be located within a predetermined tachometer count range from the home position. The detector/sensor is used to precisely locate each cartridge. The precise tachometer position is stored and the cartridge is returned to the known location. As a result, tolerance accumulation effects are eliminated in the system.

Abstract: The barrel shifter of the present invention comprises a latch circuit of (m+n) bit, a register for indicating an effective bit length retained in the latch circuit, a selector for connecting the variable length code of maximum n bit with the latch circuit and a counting circuit for counting shifting number. In this invention, the latch circuit is divided by k bit, and the selector is controlled so as to shift bits of difference between the value lastly shifted and the value of the register, and data is retained at the latch circuit. When the value of register exceeds m, the selector outputs m bits to the latch circuit and the data at the latch circuit is shifted m bits.

Abstract: A computer system with power budgeting for removable devices is disclosed comprising a nonvolatile memory that contains a power resource table for storing a power consumption indication for at least one resident device for the computer system. The computer system further comprises a removable device that contains a card information structure that stores a power consumption indication for the removable device. A processor executes a power management driver that allocates a power budget to the removable device according to the power resource table and the card information structure. The power management driver updates the power: resource table to indicate the power budget to the removable device.

Abstract: One data transmitter for transmitting a broadcast data onto an outside data bus and data receivers, whose number is "n", for individually receiving the transmitted broadcast data are provided. A single error signal line is connected in common to the data transmitter and each of the "n" data receivers. Each of the data receivers notifies an error detection to the data transmitter and the other data receivers via the error signal line with a wired OR connector when its own data receivers detects an error. Being notified of the error detection, the data transmitter re-transmits the data so that all of the data receivers re-receive the data. Accordingly, re-transfer per one data at a broadcast transfer is contemplated.

Abstract: Arithmetic units are supplied with instructions from a control unit in common through an instruction broadcast bus. Each of the arithmetic units includes a process data input port, an address data input port, a process data output port and an address data output port. Address data appearing on the address ports specify addresses of a local memory. Each of the arithmetic units reads corresponding numeric data from the local memory and executes arithmetic processing in accordance with the instruction supplied from the control unit through a computing element group and a register group. In each arithmetic unit, it is possible to specify addresses of the local memory independently of each other. Each unit include circuitry for omitting an arithmetic operation on data read from the local memory when the read out data is negligible.

Abstract: A control system for a ROS scanner in which the aspect ratio and magnification of an image is controlled by precise, real-time control of the relative velocities of the polygon mirror and the photoreceptor. Values related to monitored measurements of polygon mirror and photoreceptor velocity are mathematically combined with a reference clock value and other factors to yield real-time control signals. The control signals operate the polygon and photoreceptor motors to obtain a desired magnification and aspect ratio of images created on the photoreceptor.

Abstract: An error detection method is provided for receiving input data which are attached with error detection codes and then subjected to a convolutional coding operation, subjecting the input data to an error correction Viterbi decoding operation, calculating and storing branch or path metrics and, at the time of detecting an error in the error detection codes, independently detecting either one of a plurality of error detection blocks having the error present therein.

Abstract: The filter coefficients of a digital band pass elliptic filter can be approximated to a linear function of the center frequency of the pass band width. The filter coefficients of a band pass digital filter having a predetermined center frequency and the slope of this linear function are stored in first and second memories. A central processing unit (CPU) obtains the difference between a desired center frequency and a predetermined center frequency. A multiplier multiplies the slope stored in the second memory by the difference obtained by the CPU. An adder adds each of the filter coefficients stored in the first memory to an associated one of the products output from the multiplier. The adding results become the filter coefficients for obtaining the desired center frequency. Those filter coefficients are set in a digital filter.

Abstract: In a decoding apparatus (100), overflow conditions can be determined within the same clock cycle by determining the type of operation to be performed. For time sensitive operations, a load (102) and a discharge device (105) are temporarily coupled to a dynamic decoding structure (101) of the decoding apparatus (100). The load (102) and the discharge device (105) allow the decoding apparatus (100) to stabilize within a first clock phase (114) of a clock cycle. Thus, the second phase (113) of the clock cycle can be used to determine whether an overflow condition has occurred. For non-time sensitive operations, a precharge device (104) and the discharge device (105) are operably coupled to the dynamic decoding structure (101), while the load (102) is disabled.

Abstract: In the case where a multiplier factor is a constant, if the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is larger than the number of the bits having the value of 0, a circuit for performing multiplication by using the logic NOT number of the multiplier factor, which is obtained by inverting all the bits in the multiplier factor by the logic NOT operation is generated. If the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is smaller than the number of the bits having the value of 0, the multiplier factor is divided so that an adder for adding partial products forms a well-balanced binary tree. Conversely, if the number of the bits having the value of 1 in the multiplier factor is 2 or less, an add shift multiplier for calculating partial products only with respect to the bits having the value of 1 is generated.

Abstract: A highly distributed industrial control system employs a number of separate control modules communicating together on a shared communications medium. Each module emulates one or more basic electrical parts having electrical terminals, such as switches and relays, and transmits production messages indicating the state of the parts, such as conducting current or not. A connection list for each part in each control module defines message identifiers of other parts whose production messages are received by the control module and interpreted as current flow to one or more of its parts. The control system is programmed by generating a schematic on a programming terminal showing connections of terminals on symbols of the parts such as would represent actual wiring of the emulated parts. A parts layout diagram is used in conjunction with the schematic to identify each part to a physical module.

Abstract: A transform coefficient matrix is factorized in two submatrices of coefficients. One submatrix is applied to a subword formed of selected input data points and the other submatrix is applied to a subword formed of other selected input data points. This provides two sets of transformed output words. These transformed output data words are then combined. The two subwords may include, respectively, the odd data points and the even data points of the input data word. Alternately, the two subwords may include the high order data points and the low order data points. The transform performed by these operations may be the forward discrete cosine transform or the inverse discrete cosine transform. The submatrices of coefficients may be applied to differences of data points as well as to sums of data points. The differences and sums of data points may be applied to the submatrices of transform coefficients by the use of respective circular buffers.

Abstract: A serial-to-parallel type multiplier capable of performing a highspeed calculation with high precision includes a selection circuit provided in a unit calculation block, an output of this selection circuit being input into an adder, and the selection circuit selectively outputs either a logic product between a multiplier bit to be input into this unit calculation block and a multiplicand bit input into this unit calculation block within one unit time period or a logic product between a multiplier bit to be input into this unit calculation block and a multiplicand bit input into this unit calculation block within a unit time period prior to the above-described one unit time period.

Abstract: A sampling frequency converter capable of performing an operation of multiplications and additions at a lower speed and realizing with a small amount of hardware.

Abstract: The tolerable maximum feed rate Fd is calculated in real time during operation based on the tolerable minimum moving time Ta to be determined by the data interpretation and the moving distance L of each machining block. If the command feed rate Fc exceeds the tolerable maximum feed rate Fd, the actual feed rate for the block is set to the tolerable maximum feed rate Fd, thereby realizing smooth deceleration and preventing mechanical shock of the machine tool and reduction in machining accuracy. Required time for each processing element is determined in advance, the sum of processing times corresponding each element is calculated by judging the processing mode element contained in machining for each block. Then, the feed rate is controlled by determining the tolerable minimum moving time for each block based on the calculated sum of processing times.

Abstract: A track ball mechanism for an information processing apparatus is assembled integrally with a palm rest member and is attached to an input device of the information processing apparatus.