Abstract: A signal that may be represented by a band limited periodic function m(t) is transformed into its z-domain zeros using characteristics of the signal in the neighbourhood of fades of the signal, namely a bounds of the fades and the depths of the fades. The z-domain zeros are the zeros of the function in the complex plane, and represent local minimums of the function. The z-domain zeros are used to estimate the discrete spectrum of m(t), and the differential phase of m(t) is derived from the envelope of m(t) using the concept of the z-domain zeros. Also, speech is compressed based on the z-domain zeros of a signal m(t) that represents a speech signal, and knowledge of the location of fades is used in interference reduction at single moving antennas by applying a spectral resolution technique during a fade and applying notch filters to the signal to resolve the signal components.

Abstract: A high speed apparatus and method for determining the number of leading zeros or ones in a binary data field, in particular, a fixed-sized field, and further, indicating whether all of the bits of the binary data field are zero or one, is provided. The apparatus includes a plurality of detector circuits, coupled in parallel, to input different sections of the binary data field. For a leading zero detection operation, each detector circuit is configured to identify the bit location which contains the most significant "1" of the section of the binary data field which the detector inputs, and output a binary number signal representing the number of zeros leading that most significant "1". Each detector circuit also determines whether each bit location in the section which the detector inputs contains a "0" and provides a zero-detect signal representing this condition.

Abstract: In this controller, a manipulated variable is produced as a sum of a linear compensation term and a product term, the compensation term being a linear combination of a contouring error and its time derivatives, and the product term being formed by multiplying a fuzzy control term by a saturation term. This controller combines the advantages of the sliding-mode controller with boundary layer and those of the fuzzy controller, and thus represents a robust controller for a wide class of nonlinear nth-order systems.

Abstract: A system for marking an edge of a mailing piece with a desired indicia, thereby permits identification of the marked mailing piece when the marked mailing piece is stacked with other mailing pieces, usually similar mailing pieces. A computer directs which mailing piece is to be marked and activates the marking process. A group of computer controlled solenoids, with each solenoid linked to an indicia imprinting marking pad, is activated for the edge marking. Each activated solenoid forces the marking pad against the mailing piece's edge thereby marking the edge of the mailing piece.

Abstract: In a multicomputer system (MRS) with a central computer (ZR), a number of peripheral computers (PR0, . . . , PR29) signal their availability to the central computer (ZR) when starting or restarting the system. It is possible that overload situations occur during this process. According to the invention, a computer-dependent signal delay (V.sub.PR) of the availability is provided for each peripheral computer (PR0, . . . , PR29) within a predetermined time interval (T). Each peripheral computer has a specific computer number (n.sub.PR). All peripheral computers (PR0, . . . , PR29) should have signaled their availability within the predetermined time interval (T). For this purpose, the maximum number (n.sub.max) of peripheral computers (PR0, . . . , PR29) must be known and the central computer (ZR) must be able to process simultaneously an available quantity (A) of peripheral computers (PR0, . . . , PR29) that signal their availability. In this case, the computer-dependent signal delay (V.sub.

Abstract: Tile mosaics are created for architectural decorative surfaces or other purposes using mosaic design system linked with a manufacturing sequence to enable efficient design of mosaics and complex filings, implemented in a production line with elements for continuous cutting (46), drying (56), firing (58), glazing (52), glaze-firing, diamond film coating (64), application of resilient backing, labeling, and packaging (68) of matted sections of tiles (T) of ceramic or other materials, of any shape, size, or orientation, in which the tiles in a section are held together by embedded wires (39) or by bonding edge-to-edge.

Abstract: First blocks with data units are encoded or decoded in a first error protection code in an encoding or decoding device. A sub-set of data units, comprising one data unit from each first block, is encoded or decoded in a second block of the second error protection code. The data units of each first block are stored so as to be group-wise distributed among different pages of a paged memory. On each page data units from different first blocks are stored, so that upon reading of the data units of the sub-set the data units can also be written again so as to be group-wise distributed among different pages. The number of necessary page address changes is thus minimized.

Abstract: A feedback controller configured to automatically tune a control system by determining proportional gain, integral time and/or derivative time control parameters based on estimates of process time delay, process time constant and process gain values which are monitored by the feedback controller. The feedback controller further determines control limits for estimating the process time delay based on the resolution of the sampled values of the process output and the standard deviation of the process output during the initial steady-state condition. The feedback controller also estimates characteristic areas for a first-order response based on a first-order plus time-delay model to determine process time constant and process gain values. These process time constant, process gain and process delay estimates are translated into proportional gain, integral time and/or derivative time control parameters based on design relations of the particular feedback controller.

Abstract: A method and apparatus for performing finite impulse response filtering in real time is accomplished by taking advantage of symmetrical FIR coefficients of FIR filters in audio equipment. Due to the symmetry of the coefficients, each coefficient, other than the T0 coefficient, has an almost identical counterpart. Thus, only one of the identical coefficient needs to be stored and is used in conjunction with two data points. The two data points are summed together prior to multiplication by the corresponding coefficient to produce an accumulated resultant. This process repeats for each pair of data points, and corresponding FIR coefficient, until a final resultant is obtained.

Abstract: A circuit and method for puncturing data on the transmission side of a digital communications system. The puncturing circuit includes a multiplexer circuit that receives a data stream and a delayed version of the data stream. The multiplexer circuit generates a multiplexer output which can be either a bit from the data stream or a bit from the delayed version of the data stream. A control circuit is coupled to the multiplexer circuit to select which multiplexer input appears on the multiplexer output. The control circuit selects the multiplexer output according to a predetermined puncture pattern. The control circuit may be a counter coupled to a decoder which is coupled to the multiplexer. The decoder may be specially designed to decode the predetermined puncture pattern and rate, and the counter controls the decoder's movement through the puncture pattern and rate.

Abstract: A method and apparatus for communicating serial data at very high actual and effective data rates with a high probability of detecting single and multiple bits errors, even burst errors. The method and apparatus generates at least three parity bits which are sent with each serial data word: an even parity bit taken over all the even bits (including bit 0), an odd parity bit taken over all of the odd parity bits, and a third to parity bit that is an even parity bit taken over every fourth data bit. These parity bits are generated and transmitted along with each data word. At the receiving end, the data portion of each received serial word is stored in a register. The parity bit portion of each received serial word is stored in another register within a parity bit checker. The parity bit checker generates three parity bits taken over the received data word in the same manner that the transmitted parity bits were generated.

Abstract: A pseudorandom number generator which uses linear feedback shift registers and a nonlinear function circuit and can make the conditioned output distribution of generated pseudorandom numbers uniform even if the conditioned output distribution of the nonlinear function circuit has some deviation. The generator has a shift register to which the output of the nonlinear function circuit is inputted as a serial input, an initial value setting circuit for setting random initial values to the linear feedback shift registers and the shift registers, and an adder for adding predetermined bits of the parallel outputs of the register and outputting a pseudorandom number stream. The generator can be used to generate a cryptogram which cannot be deciphered by the correlation attack method.

Abstract: A wafer positioning system determines the position of a wafer during processing by monitoring the position of the wafer transport robot as the robot transports the wafer by one or more position sensors. The wafer positioning system incorporates a transparent cover on the surface of the wafer handling chamber and two optical position sensors disposed on the surface of the transparent cover. The position sensors direct light through the wafer handling chamber to reflectors near the floor of the chamber which reflect the light back to the position sensors. A detector within the position sensor detects when the beam path from the position sensor to the reflector is uninterrupted. As wafers are transported through the chamber, the edge of the transported wafer interrupts the position sensor beam path causing the output of the position sensor to switch states. When the position sensor output switches, the position of the wafer transport robot is measured.

Abstract: The transmitted bits are coded according to the product of at least two systematic block codes. An iterative decoding is applied in order to determine, at each code word search step, a data matrix and a decision matrix which are used for the following step. The new decision matrix is determined at each step by decoding the rows or the columns of the input matrix, and the new data matrix is determined by taking account of correction terms which increase the reliability of the decoding at each iteration. The method is especially suited for use with high-efficiency block codes.

Abstract: In a wire-cut discharge machine, a workpiece fixedly mounted on a movable table is returned from the present position to a machining start position so that auxiliary objects, such as clasps for holding the workpiece, and structural objects, such as the nozzle of the wire-cut discharge device, do not interfere with each other. Relative coordinate values between the machining start position and the present position are calculated and the calculated results are displayed on a display device. The workpiece is moved in an X-direction and is then moved in a Y-direction toward the machining start position based on moving data corresponding to the calculated results.

Abstract: An automatic method for controlling a curve cutting device used for cutting a textile web along a cutting line comprises different control strategies for critical and non-critical pattern segments. In non-critical pattern segments, the cutting head of the curve cutting device is controlled on the basis of the detected position of said cutting head relative to the light gap of the textile web. If, however, critical pattern segments are reached, the mode of operation will be changed over, whereupon the cutting head will be controlled on the basis of stored relative movement values from the moment the end of the preceding, non-critical pattern segment is reached.

Abstract: An error detecting and correcting apparatus includes a unit for receiving an encoded word including a plurality of b-bit bytes (b is an integer not less than two) and generating syndrome from the encoded word according to a first parity check matrix H.sub.1, and a unit for correcting errors in the received encoded word based on the syndrome.

Abstract: A process control system having a feedback controller, at least one manipulated variable and one controlled variable with a feedforward loop is provided. Independent feedforward control is incorporated into the feedback controller by defining a feedforward control funnel and a feedback control funnel for each controlled variable, specifying a time T.sub.FF in which the disturbance is to be eliminated and a time T.sub.FB in which the controlled variable is to reach a steady state value, respectively. The shorter of the feedforward control funnel and the feedback control funnel is selected. If T.sub.FF is less than T.sub.FB, the feedback control speed is compensated such that the feedback controller speed is not increased. If T.sub.FF is greater then or equal to T.sub.FB, no compensation is performed, thereby effectively providing independent tuning parameters for the feedforward control solution and the feedback control solution.

Abstract: A FIR filter based upon squaring accumulates the sum of the squares of the samples of a digital input signal. The samples also are added to respective filter coefficients, squared and accumulated in a plurality of filter stages. The sum of the squares of the samples are subtracted, together with a constant that is the sum of the squares of the filter coefficients, from the output of the last filter stage to produce an output signal that is divided by two to produce the samples for a digital output signal.

Abstract: A floating point binary number that is to be converted to a fixed point representation, or a fixed point number to be reduced in precision, is originally located in a source register. A conversion mechanism connects the source register to a destination register. After the conversion the least significant bit of the fixed point representation may deliberately retain an indication of the existence of less significant non-zero bits that were truncated. When such retention is desired it is accomplished by forcing that least significant bit to be a one if the fractional portion of the converted number is zero and there were such truncated non-zero bits of lesser significance. To do this the direction and amount of mantissa shift needed during conversion are inspected to reveal which bit positions in the original floating point number are going to be truncated. An array of two-input AND gates has one AND gate per possible truncated bit.