Abstract: A synchronization circuit for use in a bridge connecting an emitter bus operating on an emitter clock frequency to a receiver bus operating on a receiver clock frequency is provided. The synchronization circuit is responsive to a control signal generated by memory status means coupled to a memory which temporarily stores data transmitted from the emitter bus to the receiver bus. The control signal representative of the status of the memory is reflecting asynchronous read and write operations within the memory. The resultant signal output from the synchronization circuit is a one clock synchronized signal such that rising and falling transitions are synchronized to the receiver bus clock frequency.

Abstract: Use of a Thin protocol in an AV/C command is made possible. A TO (Thin Output) plug that conforms to the Thin protocol is provided in a disk camera which transmits data. In a similar manner, a TI (Thin Input) plug that conforms to the Thin protocol is provided in a printer which receives data.

Abstract: The invention relates to an electronic system, in particular a mobile data capture and data output device in which the electronic system has a processor (1) and at least one i/o unit (8) with a control unit (7), and in which the processor (1) is connected to the control unit (7), and the control unit (7) is connected with at least one i/o unit (8). The electronic system is switched to a standby-mode, in which a control software unit (2), which is connected to the processor (1) and the control unit (7) executes part of the processor work, and the control software unit (2) monitors the time when data input from at least one i/o unit (8) commences. If commencement of data input is registered the steps needed for data capture are initiated and concluded before the data input is terminated.

Abstract: A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy that all of the functional units on the die are not, and do not need to be operational at a given time in the execution of a computer program that is controlling the microelectronic device. The present invention on a very rapid basis (typically a half clock cycle), therefore, turns on and off the functional units of the microelectronic device in accordance with the requirements of the program being executed. This power down can be achieved by one of three techniques; turning off clock inputs to the functional units, interrupting the supply of power to the functional units, or deactivating input signals to the functional units.

Abstract: A unified memory system includes a processor, a memory controller, a plurality of bus transactor circuits and a shared memory port. A processor bus is coupled between the processor and the memory controller. A first multiple-bit, bidirectional system bus is coupled between the shared memory port, the memory controller and the plurality of bus transactor circuits. A second multiple-bit, bidirectional system bus is coupled between the memory controller and the plurality of bus transactor circuits.

Abstract: A monitor having a microcomputer for performing a serial peripheral interface (SPI) communication with a personal computer (PC) which can improve the communicability between the PC and the monitor. The monitor includes an interface using in common one communication type utilizing a serial clock and a serial data through a printer port of the PC and the other communication type utilizing RS232C through a COM port of the PC, and data is stored in or read out from the microcomputer through the interface. The interface performs an input/output of the serial data utilizing the printer port and the COM port.

Abstract: A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. The host CPU and video controller form part of a server arranged within a distributed computing system. An administrator situated at the remote terminal can retrieve select video screens produced during server operations to determine information regarding the server configuration and possible causes of server failure or future failure. The sequence of video screens thereby represent video screen changes stored upon a server controller adapted for coupling to the server expansion bus. The video screen changes represent a sequence of video screen changes occurring prior to server failure or after server reset. Those changes provide beneficial information to an administrator located remote from the server, and allows the administrator to communicate with the server using several possible communication protocols.

Abstract: In one embodiment, the invention includes an apparatus, such as a bridge, for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus a task priority update transaction including data representative of a task priority designation of a processor of the computer system, and to provide a signal responsive thereto. The apparatus also includes remote priority capture logic to receive the signal responsive to the task priority update transaction and update contents of the remote priority capture logic in response thereto. In another embodiment, the invention includes an apparatus for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus an end-of-interrupt (EOI) transactions and to provide an EOI signal responsive thereto.

Abstract: A management communication bus for enabling management of network devices in a network system. The network system includes at least one bus master device and at least one slave device, where the bus master and slave devices are distributed within the network devices. Each network device includes a slave device or a bus master device or both. The bus includes several conductors for state signals for defining four states for arbitration, for slave identification, for asserting an address and for asserting data corresponding to the address. The bus further includes several conductors for data signals for transferring information data depending upon the different states, where the information data includes bus request, slave identification, the address and the data corresponding to the address. Each bus master includes an interface to the bus to step through each of the states for controlling each cycle. Each bus master and slave device includes an identification number with a predetermined priority.

Abstract: According to the present invention, an apparatus for prioritizing access to external devices includes a request queue suitably arranged to store any number of reqeusting device requests of the external devices, a request queue controller unit coupled to the request queue suitably arranged to fetch any of the requests stored therein, a responds queue suitably arranged to store any number of responses from the the external devices.

Abstract: A method for controlling physical security of a computer removably coupled to a network wherein a security administrator associated with a server invokes a timer in a client computer and disables the client computer if the computer is not operated within the network with a frequency preset by the security administrator. Techniques are provided in the client computer to inhibit breach of the security of the timer.

Abstract: A distributed storage system provides a method and apparatus for storing, retrieving, and sharing data items across multiple physical storage devices that may not always be connected with one another. The present invention comprises one or more ‘partitions’ on distinct storage devices, with each partition comprising of a group of associated data files. Partitions can be of various types, and the partitions of the various clients may, at various times, be merged into a consolidation file or a file resident within another partition. The system resolves conflicts between two or more clients to determine which updates, if any, should be stored in a library partition. The flexible, self-referential table of the present invention may store any type of data, both structured and unstructured, and provides an interface to other application programs. The table of the present invention comprises a plurality of rows and columns.

Abstract: The present invention comprises a system for implementing pseudo delayed transactions through a bridge in order to guarantee access to a shared device. The system of the present invention functions in a computer system having a plurality of busses, including a first bus on one side of a bridge and a second bus on another side of the bridge. A first initiator device and a second initiator device are coupled to the first bus. The first and second initiator devices are both adapted to request ownership of the first bus and receive a respective first and second grant signal responsive thereto. A target device is coupled to the second bus. The bridge is coupled to the first bus and the second bus. The bridge is adapted to implement data transactions between the target device and the first device or the second device.

Abstract: A method and implementing computer system is provided in which PCI bus load conditions are detected and dummy loads are selectively switched into the PCI bus under light load conditions in order to avoid voltage overshoot problems. Load control logic receives input signals representative of the presence or absence of adapters connected into PCI slots. The load control logic is connected to load control switches. The load control switches are arranged to selectively connect to the PCI slot or to a dummy load. The load control system is selectively operable, by controlling the load switches, to connect dummy loads into empty PCI slots to dampen the bus when light load conditions are detected to exist on the PCI bus. In a PCI system hot plug environment, the system is operable to quiesce the slot being hot plugged so that the adapter can be removed or inserted into a PCI slot while maintaining acceptable PCI bus loading conditions.

Abstract: A priority encoder circuit (10, 60) is provided. The priority encoder circuit (10, 60) includes a plurality of inputs (38, 90) and outputs (40, 92). The number of inputs (38, 90) equals the number of outputs (40, 92), and each input (38, 90) corresponds to one output. Each input (38, 90) receives a signal that indicates whether the input (38, 90) has been selected. The priority encoder circuit (10, 60) also includes circuitry (50, 100) that generates a signal at the output (40, 92) corresponding to the input (38, 90) having the highest priority that receives the selection signal.

Abstract: A distributed computer system includes a host CPU, a network/host bridge, a network/I/O bridge and one or more I/O devices. The host CPU can generate a locked host transaction, which is wrapped in a packet and transmitted over a network to the remote I/O device for replay. The remote I/O devices can generate interrupts. The interrupt is wrapped in a packet and transmitted to the host computer for replay as an interrupt. The host CPU then executes the appropriate interrupt service routine to process the interrupt routine. The remote location of the I/O device with respect to the host CPU is transparent to the CPU and I/O devices. The bridges perform wrapping and unwrapping of host and I/O transactions for transmission across a network.

Abstract: Disclosed is a method far backing up memory and calendar, which has the steps of: providing a back-up power source for the calendar separated from the back-up power source for both the memory and the calendar; and continuing to back up the calendar by the separated back-up power source even after stopping the backing-up of the memory. Also disclosed is a circuit for backing up memory and calendar, which has a first power source circuit to supply back-up current to both the memory and the calendar; and a second power source circuit to supply continuously back-up current to the calendar when the supply of back-up current to the memory stops due to reduction in the capacity of the first power source circuit.

Abstract: Round-robin arbitration circuit selects in clock cycle channel contending for arbitration; each arbitrated channel having channel number in sequence of channel numbers. Channel is designated as currently arbitrated; designated channel having designated number. Channels are masked from arbitration with designated channel, such that designated and unmasked channels are arbitrated to select channel. Channels having numbers sequenced after designated number are masked from arbitration, and channels having, numbers sequenced earlier than designated are also masked from arbitration. During subsequent cycle, designated channel is shifted to next channel in sequence of channel numbers by incrementing designated number. When designated number is last in sequence, designated channel is shifted to next having first number in sequence.

Abstract: A system for assigning unique addresses to a series of electronic units in an in-flight entertainment system. The electronic units are connected via an interconnect bus and a keyline wire. During initialization of the system, each electronic unit is enabled via the keyline. After an electronic unit is enabled, the interconnect bus transfers a unique address to the electronic unit and instructs it to ignore future address write signals. This procedure is repeated for each electronic unit in the series of electronic units. The procedure terminates when the last electronic unit requiring an address has been assigned an address.

Abstract: A method for reducing power consumption in a computer system is provided wherein the computer system includes a system bus interface connected by a signal line to a power supply and/or clock circuitry for the central processing unit, each having the capability to change the characteristic of its output responsive to the signal line for placing the central processing unit in a low-power consuming state. The system bus interface chip further including a storage location and counter for storing the type and quantity of interrupt assertions during the period of time when the central processing unit is in the low power consuming state.The system software determines the desired period of time to put the central processing unit into the low-power consuming safe and does not return it to normal power consuming state until the time period has expired, a non interval clock interrupt is asserted, or another critical event occurs that needs immediate CPU attention.