Abstract: A frame timing acquisition system and method are provided including a correlator for comparing a first fixed length subsequence of bits of a received bitstream to a predetermined sync word. A CRC check circuit is provided for, in response to the correlator determining that the first fixed length subsequence of bits matches the predetermined sync word, if a third fixed length subsequence of bits of the bitstream is a cyclical redundancy code parity word formed from a second fixed length subsequence of bits of the bitstream. A decision circuit is also provided for identifying boundaries of a frame of the received bitstream in response to the CRC check circuit determining that the third fixed length subsequence of bits is a cyclical redundancy check parity word of the second fixed length subsequence of bits. According to the inventive method and system, a sync word need be identified in only a single slot of the frame in order to acquire the frame timing.

Abstract: An ATM switching system architecture of a switch fabric-type is built of, a plurality of ATM switch element circuits and routing table circuits for each physical connection to/from the switch fabric. A shared pool of memory is employed to eliminate the need to provide memory at every crosspoint. Each routing table maintains a marked interrupt linked list for storing information about which ones of its virtual channels are experiencing congestion. This linked list is available to a processor in the external workstation to alert the processor when a congestion condition exists in one of the virtual channels. The switch element circuit typically has up to eight 4-bit-wide nibble inputs and eight 4-bit-wide nibble outputs and is capable of connecting cells received at any of its inputs to any of its outputs, based on the information in a routing tag uniquely associated with each cell.

Abstract: In a bridge for interconnecting local area networks, header detectors are associated respectively with the LANs for detecting a packet header contained in a packet transmitted from the associated LAN to a destination LAN. Registration tables are associated respectively with the LANs to store information representing packets which are to be protected from interference by other packets. Comparators are respectively associated with the header detectors as well as with the registration tables for comparing the packet header detected by the associated header detector with the information stored in the associated registration table to detect a match or mismatch. Gate circuits are associated respectively with the comparators for responding to the match for preventing the other packets from being forwarded to the destination LAN and responding to the mismatch for allowing the other packets to be forwarded to the destination LAN.

Abstract: Each of a plurality of terminals in a two-way communications system includes a series of counters establishing a plurality of time slots synchronized to a downstream reference parameter. Upstream transmissions are effected by each terminal in one or more of the time slots which are defined by a downloaded message as comprising either a reserved slot or a contention slot. The downloaded message, which may also establish terminal transmission power levels and retransmission backoff algorithms for contention time slots, is derived on the basis of the population of subscriber terminals and the usage of the upstream channel.

Abstract: All the information sections of a processed data structure, including pre-header, tail and extra section, header and payload, can be selectively copied in a node of a communication network by means of a copy mask (12) associated with a copy block (11). A combination of an insert block (14) and an insert mask (15) is used for selectively writing to all the information sections in the data structure. In order to increase the capacity of the data structure, the length of the pre-header or tail can be increased. In the path between an input interface (10) and the insert block (14) there is an adjustable delay block (13) into which the data structure can be copied as a whole. A microprocessor (25) is coupled to all the processing units (10)-(17) and (22)-(24) of the system and serves for presetting the two masks for selecting the information to be copied and inserted.

Abstract: An Asynchronous Transfer(ATM) network comprising a plurality of ATM switches may be arranged so that it receives calls from Synchronous Transfer Mode (STM) switches that employ out-of-band signaling such that the ATM switches communicate telephone call signaling information between each other and the STM switches via an out-of-band signaling network associated with the ATM network and interface with out-of-band networks associated with the STM switches.

Abstract: An improved method and apparatus for achieving ping-pong communication over a single channel comprises a circuit (located at each communication station) which adjusts the transmission frequencies of two or more communicating stations such that each communicating station is transmitting at the same frequency as the other communicating stations. Additionally, the circuit provides a time delay between data receipt and data transmission at a given station such that data is not transmitted from the given station when data is being received by the given station. In the preferred embodiment cross coupled phase-lock loops are employed and the delay provided is such that a data pulse is transmitted half way between the receipt of two consecutive data pulses.

Abstract: A communication system having a communication network, such network having a plurality of communication paths interconnected at various nodes of the network. A plurality of subscriber units is adapted to exchange information through the network. A computer is provided having a processor and a memory, such memory being adapted to store programs to enable the processor to control the information exchange among the plurality of subscriber units. The memory stores an operating system and at least one applications program, the operating system being adapted to manage interfacing between the application program and the system. One of the application programs enables the processor to convert a modulation format of one of the subscriber units into another information transmission protocol of the network.

Abstract: A telecommunication network node is proposed which provides a novel solution to the realignment of payload of an input datastream (IN) within an output datastream (OUT) after dismantling the former. The present network node thereto generates from the payload of the input datastream (IN) data units (MSCI) some of which include a time label (TL) indicative of the moment at which they are derived. These data units (MSCI) are stored in a buffer (BM) from which they are read at a varying rate determined to track the input data rate and constituting the output data rate. This tracking is achieved by using the time labels to calculate a node delay, i.e. the delay between the derivation and the reading of a data unit, and by changing the above rate as a function of this node delay in order to keep it within predetermined bounds.

Abstract: An ATM/MPEG system receives individual MPEG programs of different constant bit rates from a plurality of servers. The individual programs are converted into ATM cells which are transmitted along an ATM network at a constant bit rate. The ATM cells are received and arranged into queues of the individual programs. A microprocessor prioritizes the queues based upon the bit rates of the MPEG programs. The queues are multiplexed to 16 VSB modulators based upon their priority assignments with the highest priority queues being sent to the modulators in preference to lower priority queues.

Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

Abstract: A land mobile radio communication system has a plurality of cell sites, each of which typically has a plurality of repeaters. The over-the-air radio communications between the cell site repeaters and the mobile radios in the system include both a voice component and a data component. The data component is carried as low-frequency subaudible information. Communication channels are provided between the radio users at each site as well as between users at different sites and between mobile radio users and the public telephone network. Within a cell site, the transmitted and received communications are digitized and passed through serial buses in a time multiplex fashion. The digitized voice is transferred between time slots to provide the required switching function. The system includes operational software to provide direct inward dial telephone number recognition, automatic voice prompts for a user entering a new cell, call priority override, fraud control for radio fleets and a dynamic control channel.

Abstract: An ATM switching system architecture of a switch fabric-type is built of, a plurality of ATM switch element circuits and routing table circuits for each physical connection to/from the switch fabric. A shared pool of memory is employed to eliminate the need to provide memory at every crosspoint. Each routing table maintains a marked interrupt linked list for storing information about which ones of its virtual channels are experiencing congestion. This linked list is available to a processor in the external workstation to alert the processor when a congestion condition exists in one of the virtual channels. The switch element circuit typically has up to eight 4-bit-wide nibble inputs and eight 4-bit-wide nibble outputs and is capable of connecting cells received at any of its inputs to any of its outputs, based on the information in a routing tag uniquely associated with each cell.

Abstract: A self-routing exchange which includes switch modules connected in multiple stages. A synchronous transfer mode (STM) circuit switch module, which is capable of changing over a connection relationship between incoming highways and outgoing highways, is provided between the multistage-connected switch modules and self-routing switch modules. Asynchronous transfer mode (ATM) switch modules are provided as switch modules in preceding and succeeding stages of the circuit switching module. In dependence upon the number m of self-routing switch modules, a controller sets, by means of software, the connection relationship between the incoming and outgoing highways in each of space switches incorporated within the circuit switching module. As a result, the total mn-number of incoming highways from the self-routing switch modules are connected to respective ones of mn-number of outgoing highways set by the controller.

Abstract: A method and apparatus for limiting switching oscillations on an ISDN line interface circuit may be accomplished by sensing the current provided to the primary winding of the line coupling transformer (14). When the primary current is in a first pre-determined range, a first control signal (64) is generated such that a first impedance is applied across the primary winding during a trailing edge of the transformer switching. When the primary current is within a second pre-determined range, a second control signal (66) is produced that causes a second impedance to be imposed across a primary winding during the trailing edge of the transformer switching.

Abstract: A system for full duplex real time two-way voice and data communication between a pair of computer terminal locations is disclosed. Analog voice signals are converted to digital form at one terminal location and those digital signals are interleaved with other digital information for transmission to the other terminal location. A value for the number of bytes in a data packet is first established, and then values for the number of bytes and the location dedicated to the transmission of voice information, control information, and data transmission within such fixed size data packets is established. Thereafter, a sequence of data packets with synchronization bytes in the voice byte locations is transmitted from each computer terminal location and received by the other of the terminal locations. Upon receipt thereof, an acknowledgement of the receipt is transmitted back to the originating location to indicate the establishment of synchronization between the two locations.

Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. A second embodiment of the invention partitions the system into a base subsystem, a communications link and a remote subsystem, collectively referred to as a distributed architecture system. The distributed architecture system provides all of the performance monitoring and testing capabilities of the existing access system. The distributed architecture system provides a mechanism to transport a plurality of asynchronous and rate independent signals across the link to permit remote testing of digital and voice DS0 frequency circuits. In the preferred embodiment, the link that connects the base to the remote system is a standard DS1 channel.

Abstract: A system for isolating the direction of communication errors in the local loop of a digital data network is described. A Network Interface Unit (NIU) located at the customer premises typically has a loopback feature, allowing for Bit Error Rate Tests (BERT) to be performed on the local loop from a remote test system located on the data network. The NIU loopback test isolates transmission problems at the customer premises from problems on the local loop. The present invention adds test pattern generation capability to the NIU, allowing the remote test system to determine whether the transmission problem on the local loop is in the network to customer premises direction or in the customer premises to network direction.

Abstract: A new dimension for growth is presented for the generalized growable packet switch architecture. That dimension is time and by rolling routing requests around a distributed out-of-band controller ring, ATM cell traffic can be controlled and spread across two time intervals. The rolling of routing requests and the resulting time spreading of the cell traffic through the distribution network averages out bursts and localized hot spots, thereby reducing blocking and improving cell loss probabilities with only small increases in hardware cost and complexity.

Abstract: A communication control unit connecting a terminal and a network temporarily disconnects a circuit of the network without ending a session, when no data is received from the network or when no data is transmitted to the network. In response to an occurrence of the transmitted data in the terminal or in response to an occurrence of a request for the connection of the circuit, the temporarily disconnected circuit is re-connected so that the session is resumed.