Abstract: A ring oscillator based voltage controlled oscillator (VCO) is disclosed. The VCO includes a set of delay cells connected to each other in a ring configuration. Each of the delay cells includes a source-coupled input transistor pair, a current-steering transistor pair and a pair of load resistors. The source-coupled input transistor pair receives a pair of differential voltage inputs. The load resistors, which are connected to the source-coupled input transistor pair, provide a pair of differential voltage outputs. The current-steering transistor pair, which is connected to the source-coupled input transistor pair, receives a pair of differential bias voltage inputs. The output frequency of the VCO is directly proportional to the differential bias voltages at the pair of differential bias voltage inputs.

Abstract: Control circuitry is disclosed including an oscillator operable to generate an oscillator signal. A frequency of the oscillator signal increases as an amplitude of a first voltage increases up to a threshold, and the frequency of the oscillator signal decreases as an amplitude of the first voltage exceeds the threshold. The oscillator is operable to generate a foldover signal indicating when the frequency of the oscillator signal is decreasing due to the first voltage exceeding the threshold.

Abstract: The invention relates to pulse width modulator system (PWMS) comprising a modulator system input (MI),a modulator output (MO), an amplitude distribution filter (ADF) ,and a pulse width modulator (PMOD), wherein said amplitude distribution filter (ADF) establishes an intermediate output signal (OS) by modifying the level of the amplitude distribution of an input signal (IS) within at least one predetermined amplitude range of said input signal (IS), said input signal (IS) being received from said modulator system input (MI), and wherein said pulse width modulator (PMOD) provides a modulator output signal (MOS) on said modulator output(MO) on the basis of said intermediate output signal (OS).

Abstract: A fast lock circuit for phase lock loop comprising a frequency detector, a phase frequency detector, a logic unit and a corresponding charge pump for the frequency and the phase frequency detectors. Embodiments of the present invention use the logic unit to relay signals from the phase frequency detector circuit to the charge pump when the PLL is in lock. The logic circuit relay signals from the frequency detector circuit before the PLL is in lock. As a result, a constant current is supplied to a large loop filter capacitor before lock. In one embodiment, additional logic circuit may be used to maximize the output current. Therefore, using the logic circuit to supply constant current charges the large loop filter capacitor continuously and avoids a slow down in charging the large loop filter. Accordingly, current is no longer wasted and the lock time is improved.

Abstract: A temperature detection circuit (18) detects temperature around an oscillation circuit (20) equipped with voltage variable capacitors (23, 24). According to its temperature detection signal, a temperature compensation circuit (30) produces a voltage signal as a temperature compensation signal. That voltage signal is supplied to the voltage variable capacitors (23, 24) in order to sustain oscillation frequency of the oscillation circuit (20) at a substantially constant level. When a switch element (1) is, turned on by a non-TCXO signal, both terminals of each voltage variable capacitor (23, 24) are brought to the same potential (ground potential). Consequently, each voltage variable capacitor has a predetermined capacitance and temperature compensation function is made ineffective. In that state, initial frequency regulation is performed under normal temperature.

Abstract: Techniques to compensate for nonlinearity of a tuning function of an oscillator are described. The tuning nonlinearity of the oscillator may be modeled as a disturbance input to the oscillator and may be compensated with an equal but opposite disturbance. In one design, a nonlinearity correction signal to compensate for the tuning nonlinearity may be generated, e.g., based on a phase error signal in a phase-locked loop (PLL) and a scaling factor determined adaptively. The nonlinearity correction signal may compensate for the n-th (e.g., second) order tuning nonlinearity, and an n-th order (e.g., squared) modulating signal may be used to derive the scaling factor and the nonlinearity correction signal. A control signal for the oscillator may be generated based on the nonlinearity correction signal and possibly one or more other signals. The control signal may be applied to the oscillator to adjust the oscillation frequency of the oscillator.

Abstract: A crystal oscillator circuit includes a capacitive load stage coupled to a crystal; an amplifier stage including an amplifying transistor coupled to the crystal and to the capacitive load stage for establishing an oscillation signal at the amplifier stage output and a bias generator stage coupled to the amplifying transistor; an amplitude control stage to control the amplitude of the oscillation signal; a pick-up stage coupled to the amplifier stage and to the crystal to generate an oscillator output signal. The bias generator stage is configured as a degenerated common source amplifier.

Abstract: A floating DC-offset circuit for a phase detector. The circuit may provide a floating DC-offset to the phase detector, or to the voltage-controlled oscillator of the phase-locked loop. The circuit includes a voltage comparator, clock, digital resistor, and offset line to a DC-offset branch of the phase detector. The voltage comparator detects when the voltage at the output of the loop filter of the phase-locked loop has gone outside of a designated range, and activates the clock when the voltage is outside the designated range. The clock emits impulses that are counted by the digital resistor. The digital resistor shifts DC-offset at the DC-offset branch of the phase detector. The new DC-offset level is maintained once the loop filter output voltage has returned within the designated range. In an alternate embodiment, the DC-offset branch is connected to rough-tuning input of a wide-tuned voltage-controlled oscillator.

Abstract: A self-sustaining ultra-high frequency oscillator and method enable the ability to oscillate and output a signal. A balanced bridge circuit is utilized to null an embedding background response. A first vibrating nanoelectromechanical (NEMS) beam resonator is part of one of the branches of the balanced bridge circuit and determines the frequency of the oscillator's output signal. A feedback loop establishes and sets oscillation conditions of the oscillator's signal. Further, the feedback loop connects an output of the first resonator to an input of the balanced bridge circuit.

Abstract: The crystal oscillator has a configuration where circuit elements including a crystal unit are arranged on a mounting board comprising external terminals, opening end faces of a concave metal cover are made to touch the surface of the mounting board, clearances from the opening end faces are comprised in the central regions at both ends in the width direction of the metal cover, protruding parts, which extend from the opening end faces and have a protrusion on an inner face, are comprised at both ends in the longitudinal direction of the metal cover, and each of the protruding parts is elastically inserted in a groove provided on both side faces in the longitudinal direction of the mounting board 1 and bonded by solder, wherein the tip side of each protrusion is thrust and bites into a metal film provided in the groove.

Abstract: The present invention relates to a control method for the operation modes of an oscillator and the apparatus thereof, for which the method and the apparatus can be applied to the electronic circuits with multi-operation modes of the oscillator so as to correctly choose the desirable oscillator operation mode. Furthermore, an oscillator checking circuit sets up the oscillation mode automatically and judges if the oscillator operates properly. Hence, there is no need for the user to set up the oscillator operation mode manually.

Abstract: Methods and systems for modulating an input electrical signal are disclosed and may comprise modulating input signals utilizing a digital Class-D modulator and generating a digital output signal that is proportional to the input signals. The digital Class-D modulator may be comprised of four stages. To avoid integrator saturation, the output of at least one integrator stage may be limited by utilizing limiters in integrator feedback loops. The digital Class-D modulator utilizes a pulse width modulation technique. For increased signal to noise ratio (SNR) at a desired output power, the magnitude of a triangular waveform oscillator voltage may be greater than the magnitude of an integrated input signal. The digital output signal may be fed back to an input of at least one of the four stages in the digital Class-D modulator. The triangular waveform oscillator frequency may be adjusted to match desired output frequency.

Abstract: The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.

Abstract: An apparatus and method fore harmonic characterization and ratio correction of device mismatch between coarse and fine varactor tuning devices within a segmented unified varactor bank of an (RF) digitally controlled oscillator (DCO). The DCO is divided into an MSB bank, LSB bank and sigma-delta (SD-LSB) bank. Any ratio mismatches between MSBs and LSBs are digitally calibrated out using a DCO step-size pre-distortion scheme wherein LSB steps are adjusted to account for ratio mismatch between the MSB/LSB step sizes. A harmonic characterization technique is used to estimate the mismatches in the minimal size CMOS tuning varactors of a digitally controlled RF oscillator (DCO), wherein nominal ratio mismatch between the MSB and LSB devices is estimated using hybrid stochastic gradient DCO gain estimation algorithms. The nominal ratio mismatch and the mismatches in MSB and LSB banks are used to determine average MSB/LSB mismatch which is then used to correct the LSB steps.

Abstract: A voltage controlled oscillator has a reference voltage generation section for generating a plurality of reference voltage based on a power supply voltage. Reference voltages Vref1, Vref2, and Vref3 are inputted to variable capacitance circuits A, B, and C, respectively. Reference voltages Vref1, Vref2, and Vref3 each has a fixed value, and a difference between the first reference voltage Vref1 and the second reference voltage Vref2 and a difference between the second reference voltage Vref2 and the third reference voltage Vref3 represent values different from each other. A control voltage Vt for feedback-controlling an oscillation frequency is inputted to each of the other of the terminals of the variable capacitance element of each of the n variable capacitance circuits such that the control voltage Vt having the same value is inputted to the each of the other of the terminals.

Abstract: A synthesizer arrangement includes an oscillator, a phase detector, and a loop filter that form a phase-locked loop. The loop filter is coupled to a control unit to activate a respective set of internal states out of a plurality of sets of internal states.

Abstract: A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.

Abstract: The present invention relates to an oscillating circuit arrangement having a resonating arrangement with a first resonance frequency (coo) comprising a voltage controlled oscillator arrangement. It further comprises a tunable filter arrangement connected to the source node of said voltage controlled oscillator (VCO) arrangement. Said filter arrangement particularly comprises an equivalent current source resonating at a second resonance frequency c?f, the second resonance frequency being a multiple n, n=1 or 2 of said first resonance frequency (?>o), n being equal to the minimum number of switch transistors required for oscillation of said VCO arrangement. The filter arrangement particularly comprises an inductor connected in parallel with a capacitor, said capacitor being adapted to be tunable such that the phase noise of the resonating arrangement can be minimized through tuning of the filter arrangement.

Abstract: An oscillator including a substrate and a resonant tunneling diode including a gain medium provided on the substrate. The gain medium includes at least two quantum well layers and plural barrier layers for separating the quantum well layers from each other. The quantum well layers each have one of a compressive strain and a tensile strain. The plural barrier layers that sandwich the quantum well layers having the strain have a strain in a direction opposite to the direction of the strain of the quantum well layers.

Abstract: A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.