Abstract: A ring oscillator based voltage controlled oscillator (VCO) is disclosed. The VCO includes a set of delay cells connected to each other in a ring configuration. Each of the delay cells includes a source-coupled input transistor pair, a current-steering transistor pair and a pair of load resistors. The source-coupled input transistor pair receives a pair of differential voltage inputs. The load resistors, which are connected to the source-coupled input transistor pair, provide a pair of differential voltage outputs. The current-steering transistor pair, which is connected to the source-coupled input transistor pair, receives a pair of differential bias voltage inputs. The output frequency of the VCO is directly proportional to the differential bias voltages at the pair of differential bias voltage inputs.

Abstract: A fast lock circuit for phase lock loop comprising a frequency detector, a phase frequency detector, a logic unit and a corresponding charge pump for the frequency and the phase frequency detectors. Embodiments of the present invention use the logic unit to relay signals from the phase frequency detector circuit to the charge pump when the PLL is in lock. The logic circuit relay signals from the frequency detector circuit before the PLL is in lock. As a result, a constant current is supplied to a large loop filter capacitor before lock. In one embodiment, additional logic circuit may be used to maximize the output current. Therefore, using the logic circuit to supply constant current charges the large loop filter capacitor continuously and avoids a slow down in charging the large loop filter. Accordingly, current is no longer wasted and the lock time is improved.

Abstract: A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.

Abstract: A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.

Abstract: A crystal oscillator tester includes first and second test pins, first and second transistors, an indicator, a first diode, and first-third capacitors. The first test pin is connected to a power source. The collector of the first transistor is connected to the first test pin. The base of the second transistor is connected to the second test pin. The emitter of the first transistor is grounded via the indicator. The base of the first transistor is connected to the cathode of the first diode. The anode of the first diode is connected to the first test pin via the first and second capacitors one by one in series. The emitter of the second transistor is connected to a node between the first and second capacitors. The collector of the second transistor is grounded. The third capacitor is connected between the base and emitter of the second transistor.

Abstract: The invention discloses a varactor device (100) for improved temperature stability, comprising a first varactor (160) connected to a decoupling network (150). The device further comprises a voltage stabilizer (110), said stabilizer comprising a capacitor (140) and a temperature dependent capacitor (130), and in that the stabilizer comprises means for connection to a DC-feed (120). Suitably, the decoupling network (150) is connected in parallel to the first varactor (160), and the capacitor (140) of the voltage stabilizer (110) is connected in parallel to the decoupling network (150), the temperature dependent capacitor (130) of the voltage stabilizer (110) being connected in series to the diode of the voltage stabilizer (110).

Abstract: Exemplary embodiments of the invention provide a reference harmonic oscillator integrated circuit having three or more terminals, with systems and methods for calibrating the harmonic oscillator to a selected first frequency using a limited number of terminals. An exemplary apparatus comprises: a reference harmonic oscillator, a first terminal to receive a supply voltage, a second terminal to receive a ground potential, a third terminal to provide an output signal having an output frequency, and may also include a fourth terminal. One of the first, second, third or fourth terminals is further adapted for input of a calibration of the first frequency. The exemplary apparatus may enter calibration and testing modes in response to various commands such as a calibration mode signal, and may also be configured through one of the terminals for output frequency selection, spread-spectrum output, and output voltage levels.

Abstract: The present invention provides a voltage controlled oscillator having a wide frequency variation range and an oscillation frequency that shows favorable linearity with respect to control voltage. The present invention includes an amplifier circuit 21, a piezoelectric element 22 connected in parallel to the amplifier circuit 21 and forming a feedback loop, variable capacitive elements 24 and 25 respectively connected to an input terminal and an output terminal of the amplifier circuit 21 and having a capacitance value that is dependent on control voltage, and an analog operation circuit 26 that generates a control voltage Vcs based on an inputted control voltage Vc. In this arrangement, the control voltage Vc is applied to the variable capacitive element 24 and the control voltage Vcs generated by the analog operation circuit 26 is applied to the variable capacitive element 25.

Abstract: An amplitude regulating circuit for an oscillator with an input for a supply signal having an electrical quantity depending on an amplitude of an oscillation of the oscillator has a supply circuit with a control input for a first control signal and a supply output for the supply signal based on the first control signal, a reference circuit with an input for a reference supply signal having a reference quantity, a reference supply circuit with a reference control input for a second control signal and a reference supply output for the reference supply signal based on the second control signal and a comparator circuit with a first control signal output for the first control signal based on the electrical quantity and the electrical reference quantity and a second control signal output for the second control signal based on the electrical quantity and the electrical reference quantity.

Abstract: A crystal oscillator in which a temperature characteristic of an oscillation frequency is improved to omit a measurement operation of the temperature characteristic of the oscillator, and manufacturing is facilitated to reduce a manufacturing time. In the crystal oscillator, a power voltage is applied to a collector of a transistor via series connection of an inductor for resonance and a resistance, a crystal unit is disposed in a loop which returns to an emitter of the transistor from a point between the inductor L4 and the resistance, and further, in the loop, a first parallel circuit in which a stationary capacitor having a negative temperature coefficient and a stationary capacitor having a zero temperature coefficient are connected in parallel with each other is inserted between an oscillation output taking point and the collector.

Abstract: A plurality of varactors are coupled via a first electrode to a shared terminal that in turn can operably couple to a source of control voltage. A second electrode for each varactor couples to a corresponding switch, where each switch couples to at least two different voltage levels. So configured, the second electrode of each varactor can be individually connected to either of two voltage levels. This can be leveraged to control, in coarse steps, the overall aggregate effective capacitance presented by these components. At least some of these varactors can have differing corresponding capacitances, the specific values of which can be selected in order to facilitate relatively equal spacing and substantially equal rates of reactance change versus the control voltage value between aggregate-capacitive reactance ranges as correspond to differing settings for the switches at various levels for the control voltage source.

Abstract: An oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source coupled to the first current mirror branch, a capacitive element coupled to the first current mirror branch; and a resistive element coupled to the second current mirror branch. The oscillator circuit further includes a plurality of inverting elements coupled in series with one another and a transconducting element coupled to an output of the plurality of inverting elements. The transconducting element is configured to discharge the capacitive element. A latching element is coupled to latch to an output signal of the plurality of inverting elements.

Abstract: A dynamic dual domino oscillating ring circuit is described, which has multiple non-inverting dual domino circuits, each having a signal input, N and P-domino triggers, precharge and pre-discharge, N and P-domino cutoffs and an output inverter. A number of the dual domino circuits are coupled in series, the output of one feeding the input of the next, to form a dual domino chain, which form stages of the dual domino ring. A number of the stages are coupled in series, the output of one feeding the input of the next, to form the ring. The first dual domino circuit of the chain receives a signal input and the N and P triggers for the chain. Within the ring, the output of each stage feeds the input signal to the next stage and is fed back to clock an earlier stage to allow the ring to oscillate.

Abstract: An oscillator circuit may be used with controller circuits that are designed to operate with crystals, with no modifications to the pinout or firmware of the controller circuit. In some embodiments, the oscillator circuit includes an enable input that is responsive to low-amplitude transitions, which may be coupled to and driven by the crystal output signal of the controller circuit. When transitions are present on the crystal output signal, the oscillator circuit enables its clock output signal. When the controller circuit disables its crystal output signal, the oscillator circuit no longer detects transitions on the crystal output signal coupled to the oscillator circuit enable input, and disables the clock output signal.

Abstract: An oscillator circuit may be used with controller circuits that are designed to operate with crystals, with no modifications to the pinout or firmware of the controller circuit. In some embodiments, the oscillator circuit includes an enable input that is responsive to low-amplitude transitions, which may be coupled to and driven by the crystal output signal of the controller circuit. When transitions are present on the crystal output signal, the oscillator circuit enables its clock output signal. When the controller circuit disables its crystal output signal, the oscillator circuit no longer detects transitions on the crystal output signal coupled to the oscillator circuit enable input, and disables the clock output signal.

Abstract: An integrated tunable resonance circuit is provided for providing a high-frequency output signal with a frequency dependent on a control signal, comprising a parallel resonance circuit with a first inductive element and an output for providing the high-frequency output signal, a switching unit with a controlled path, and a control terminal for switching between states, whereby the switching unit is designed to exhibit a predominantly capacitive behavior in a first state and a predominantly resistive behavior in a second state, whereby the resonance circuit is designed to drive the control terminal of the switching unit as a function of the control signal. The resonance circuit has a second inductive element which can be mutually coupled to the first inductive element, whereby the controlled path is connected parallel to the second inductive element. The invention relates furthermore to a voltage-controlled oscillator and to an integrated circuit.

Abstract: An integrated resonance circuit is provided for providing a high-frequency output signal, comprising a first output for providing a first high-frequency output signal with a first frequency and a first amplitude, a first inductive unit connected to the first output, and a first capacitive unit connected to the first output. According to the invention, a second output for providing a second high-frequency output signal with a second frequency and a second amplitude is provided, whereby the second frequency matches the first frequency and the second amplitude differs from the first amplitude, and a second inductive unit, connected to the first output and to the second output, and a second capacitive unit, connected to the second output, are provided. The invention relates furthermore to a voltage-controlled oscillator and to an integrated circuit.

Abstract: An embodiment of a circuit switches between at least a first clock signal and a second clock signal in response to a corresponding switch command, and includes a selection module to select at a switch instant said second clock signal under the control of a signal selector. The circuit comprises a logic-based filter module located downstream of said selection module and configured to produce an outgoing clock signal filtered under the control of a filter signal and also includes a control module configured to receive said switch command and to send said select signal to said selection module delaying said switch instant by a first interval of time, said control module also being configured to send said active filter signal to said filter module in a second interval of time that comprises an edge of the first clock signal and an edge of the second clock signal.

Abstract: Aspects of a method and system for a fast phase-locked loop (PLL) close-loop settling after an open-loop voltage controlled oscillator (VCO) calibration are provided. A fractional-N PLL synthesizer may comprise a VCO, a phase-frequency detector (PFD), a D flip-flop, a divider, a charge pump, and a loop filter. The synthesizer may disable the PFD based on a control signal indicating the start of VCO open-loop calibration. After open-loop calibration, the synthesizer may subsequently enable a PLL closed-loop settling and may enable the PFD to control the charge pump when the input reference signal phase lags a phase of a divider signal generated by the divider. The D flip-flop may enable and disable the PFD. During open-loop calibration, the loop filter may be discharged via a leakage current in the charge pump. During closed-loop settling, the loop filter may be charged by the charge pump via control of the PFD.

Abstract: An integrated circuit radio transceiver and method therefor includes capacitive loop filter with selectable capacitive elements that are operable to adjust a signal level provided to a voltage controlled oscillator to control a frequency of an output signal of the oscillator. A plurality of switches are controlled by logic to define a discharge mode, a charge mode and charge sharing mode in which a plurality of capacitive elements share charge while generating the input voltage to the oscillator.