Abstract: A phase synchronization circuit and an electronic apparatus equipped with the phase synchronization circuit are provided. The phase synchronization circuit includes an oscillation unit, a phase comparison unit, a loop unit, a drive unit, an oscillation control signal unit, and a gain characteristic information obtaining unit. In the phase synchronization unit, a compensation signal is generated based on the gain characteristic information obtained by the gain characteristic information obtaining unit at the time of the usual phase synchronizing operation, and the drive unit is controlled by the compensation signal so that a product of the input signal-oscillation frequency conversion gain at the time of actual operation and the drive signal with which the drive unit drives the loop filter unit is constant.

Abstract: A global positioning system and integrated circuit with a differential oscillator and with a starting circuit connected to the differential oscillator, wherein the differential oscillator has a current mirror for setting an operating current through each of the two branches, the starting circuit has at least one switch connected to the current mirror, and has a starting means connected to the at least one switch, and the current mirror, the at least one switch, and the starting means are wired in such a manner that the operating current in each of the two branches of the differential oscillator is increased during a starting phase, which phase is a function of the starting means.

Abstract: An RC oscillation circuit and method capable of adjusting an oscillation frequency includes: an RC oscillator including a variable resistor and a variable capacitor, the RC oscillator generating an RC oscillating signal having a frequency determined by a resistance of the variable resistor and a capacitance of the variable capacitor; a counter counting a clock number of a reference oscillating signal corresponding to one period of the RC oscillating signal to generate a first count value, the reference oscillating signal having a preset frequency; and a frequency controller controlling a frequency of the RC oscillating signal by determining the resistance of the variable resistor and the capacitance of the variable capacitor such that a difference between the first count value and a preset second count value is smaller than a preset first critical value.

Abstract: A phase lock loop (PLL) includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the PLL. A capacitance profile for setting the frequency of the PLL at a process comer is stored. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the PLL is determined from the capacitance profile and stored capacitances. The capacitance of the PLL is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances, which is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance.

Abstract: There is provided a sigma delta modulator that outputs an output signal obtained by performing sigma delta modulation on an input signal, including: a plurality of accumulators that are serially connected; and an output signal generating section that generates the output signal on the basis of comparison result signals respectively output from the accumulators, in which each of the accumulators integrates values of signals being input and when an integration value is not less than a reference value, outputs the comparison result signal with a predetermined value and subtracts the value of the comparison result signal from the integration value, the value of the input signal is input into a first-stage accumulator, the integration value of the preceding-stage accumulator is input into the other accumulator, and at least one of the accumulators includes a low-pass filter that removes a predetermined high-frequency component in a waveform of the integration value.

Abstract: A correction processor connected to an oscillator uses precision timing signals propagated over a digital network to generate an error signal. IEEE-1588 time synchronization protocols produce precision time signals which are converted to precision interval signals. The correction processor uses the precision interval signals to count pulses of the oscillator. A correction circuit compares the counter output with a predetermined value and generates an error signal may be used to correct the oscillator or may be propagated to consumers of the oscillator. An arbitrary reference oscillator may be used to generate the precision timing signals propagated on the network, to slave other oscillators to it. The precision of the reference oscillator may be deliberately overstated to insure it is used as a master.

Abstract: Provided is a digital modulation circuit constructed with only a digital circuit. The digital modulation circuit includes: a clock generator which generates a reference clock pulse having a predetermined period; an up/down counter which generates a count value having predetermined bits by up-counting or down-counting the reference clock pulse and outputs a bit in the count value as a transmission signal; a controller which determines a counting start/end time point of the up/down counter and determine which one of the up-counting operation and the down-counting operation of the up/down counter is to be performed, according to a value of digital transmission data that is to be transmitted; and a band-pass filter which converts a waveform of the transmission signal output from the up/down counter into a sine waveform.

Abstract: A clock generator includes a current source for generating a constant current; a current mirror coupled between a supply voltage and the current source for generating a mirror current equal to the constant current multiplied by a predetermined value; and a charge control module coupled with the current source and the current mirror for charging a capacitor when a voltage thereof is lower than a predetermined threshold voltage and for discharging the capacitor when the voltage thereof is higher than the predetermined threshold voltage, thereby generating a clock signal at a predetermined frequency, wherein the charge control module adjusts the predetermined frequency by changing the predetermined threshold voltage.

Abstract: A self-biasing negative transconductance LC oscillator that uses self-biasing circuitry to regulate a current source that feeds negative transconductance circuitry and direct current (DC) bias circuitry to apply a DC bias between control inputs and outputs of the negative transconductance circuitry is disclosed. A current source setpoint is based on the voltage swing of the oscillator, which can then be controlled by the DC power supply that powers the oscillator. In one embodiment of the present invention, the negative transconductance circuitry includes a pair of p-type metal oxide semiconductor (PMOS) cross-coupled field effect transistors (FETs), which have a limit applied to their gate to source voltages. Limiting the gate to source voltages of the FETs limits the percentage of the oscillation cycle that the FETs spend in the triode region and thus reduces the noise contribution of the FETs and allows for less power consumption for a given noise requirement.

Abstract: A digitally controlled oscillator device includes a programming input, a selection input and an oscillator core with a first capacitive element which is frequency determining and programmable. The first capacitive element is coupled to the programming input that receives a first data word by which an oscillating frequency of the oscillator device is programmed with a predetermined frequency step size. The oscillator device further includes a selection unit for selecting a mode which is coupled to the selection input that receives a mode selection signal. The mode is selectable from a plurality of modes depending on the mode selection signal and each mode from the plurality of modes is characterized by a predetermined frequency step size. The digitally controlled oscillator device also includes a deattenuation amplifier.

Abstract: A code is provided which outputs a predetermined code enable signal by executing a simple control, depending on a clock signal frequency, with an optimal circuit scale. A multiplexer receives integers which are relatively prime, and outputs either of them to an adder, depending on comparator output signal. The adder adds an integer latched by the register and an integer output by the multiplexer, and outputs the result via a multiplexer to the register. The register latches and outputs the received integer to the comparator with a sampling clock signal frequency. In accordance with a threshold set based on the integers and the number of bits of the adder or the register, the comparator outputs a signal having the High state only when the output integer of the register satisfies the threshold condition. The code outputs this as a code enable signal.

Abstract: The new RTD-HBT differential oscillator circuit topology is proposed. At the nodes of the inductors and varactors in the conventional differential oscillator topology, each the RTD is attached to increase the magnitude of the negative conductance, which results in performance improvement in both the RF output power and phase noise. And, the differential sinusoidal voltage waveform which is essential for the wireless communication system are generated. In addition, the DC power consumption RTD-HBT differential oscillator circuit is similar to the conventional HBT differential oscillator due to the small DC power consumption performance of the RTD.

Abstract: A surface mount type crystal oscillator is provided with a crystal blank, an IC chip which incorporates an oscillation circuit using the crystal blank, a substantially rectangular parallelepiped container body for surface mounting which houses the crystal blank and the IC chip, and mounting electrodes provided in four corners of an outer bottom surface of the container body. Each of the mounting electrodes is provided so as to extend over a side surface of the container body as an end face electrode. At least one adjustment terminal is disposed above the end face electrode on the side surface of the container body electrically isolated from the end face electrode. The adjustment terminal is longer along the height direction of the container body than the end face electrode.

Abstract: Methods and systems for tuning an oscillator are disclosed and may comprise dividing a desired frequency range of a delay-cell based ring oscillator into segments, and tuning the delay-cell based ring oscillator over an ultra-wide frequency range by utilizing these divided segments. The enabled segment may determine the frequency range and the oscillator may be tuned within these segments. The delay may be adjusted utilizing a negative skew technique, and may be controlled by one or more digital codes. The oscillating frequency within each segment may be adjusted utilizing a control voltage or control current. The voltage or current may be buffered and utilized as a common supply of the delay cells.

Abstract: A system for reducing phase-noise in a resonant tank circuit. The system includes a single-electron device configured to inject a single electron into the oscillator circuit tank circuit. The system further includes a synchronizer coupled to the single-electron device and configured to cause the single-electron device to inject the single electron into the resonant tank circuit at a phase based on an extreme (maximum or minimum) electrical characteristic output of the resonant tank circuit.

Abstract: A ring oscillator circuit includes a ring of cascade-coupled delay stages and is controlled by a plurality of multiplexers. A feedback circuit has an input terminal coupled to an output terminal of the ring oscillator circuit. The ring oscillator circuit receives a control word and provides a clock signal on the output terminal. The ring oscillator circuit includes a control architecture including a plurality of control blocks receiving respective bits of the control word and coupled to the delay stages of the ring. Each control block has at least a bistable element capable of receiving, storing and sending a bit of the control word to a multiplexer coupled to a respective delay stage in stable operating conditions of the ring.

Abstract: A high/low voltage tolerant interface circuit and a crystal oscillator circuit using the same are provided herein. The interface circuit includes a first transistor, a bulk-voltage generator module and an bias module. The first transistor includes a gate, a first source/drain, a bulk coupled to the first source/drain of the first transistor and a second source/drain coupled to an input node. The bulk-voltage generator module is, used to determine whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to the voltage of the input node. The bias module is coupled to the gate of the first transistor. The bias module is used to provide an bias voltage to the gate of the first transistor and makes the first transistor conduct in order to control the voltage of the second source/drain voltage of the first transistor.

Abstract: The DSP MSP invention provides an implementation of programmable algorithms for analyzing a very wide range of low and high frequency wave-forms. The DSP MSP comprises a synchronous sequential processor (SSP) for real time capturing and processing of in-coming wave-form including a programmable computing unit (PCU) for controlling SSP operations and supporting adaptive signal analysis algorithms. The DSP MSP further comprises a Sequential Data Recovery from Multi Sampled Phase (SDR MSP) for a receiver of an optical wave-form.

Abstract: A digital phase locked loop (DPLL) comprising a digitally implemented voltage controlled oscillator (VCO) for producing a VCO feedback signal, a phase error counter which includes a digital phase-frequency detector for producing a first phase error signal, a quadrature phase detector for producing a second phase error signal and an adder for adding the first and second phase error signals to obtain a combined phase error signal, and two programmable dividers used to cooperatively determine the VCO feedback signal and to provide a DPLL output line sync value synchronized with an input signal.

Abstract: A hybrid modulator apparatus includes a modulator that amplitude modulates a power supply signal. A correction circuit coupled in parallel with the modulator reduces errors caused by the modulator. In one embodiment the modulator includes a digital pulse-width modulator (PWM) and a buck converter. The K most significant bits (MSBs) of N-bit input digital words are used by the digital PWM and a buck converter to generate an amplitude modulated power supply signal having a plurality of quantized voltage levels. The remaining N?K bits of each N-bit words may be used to dither the input drive to the PMW, to produce an error signal at the output of the modulator representing quantization errors caused by only applying the K MSBs to the PWM. The correction circuit compares the error signal to a signal formed form all N bits of the N-bit words in reducing the quantization errors.