Abstract: A phase locked loop (PLL) can include a test loop filter (100) that generates a control voltage (VCTRL) for input to a voltage controlled oscillator (VCO). In a test mode, a control voltage can be varied and resulting output frequencies recorded, from which an open loop bandwidth can be determined. A control voltage can be varied by enabling a switch element (104-1) that can provide a current path through load resistance (RL) of test loop filter (100). Current provided to the test loop filter can be varied according to test signals to provide a variable control voltage (VCTRL).

Abstract: A ring oscillator circuit includes a ring of cascade-coupled delay stages and is controlled by a plurality of multiplexers. A feedback circuit has an input terminal coupled to an output terminal of the ring oscillator circuit. The ring oscillator circuit receives a control word and provides a clock signal on the output terminal. The ring oscillator circuit includes a control architecture including a plurality of control blocks receiving respective bits of the control word and coupled to the delay stages of the ring. Each control block has at least a bistable element capable of receiving, storing and sending a bit of the control word to a multiplexer coupled to a respective delay stage in stable operating conditions of the ring.

Abstract: An integrated circuit device is provided having a reference ring oscillator circuit having a plurality of stages. Each stage has a logic gate and electrically connecting to a first independent voltage source. The integrated circuit device also has at least one additional ring oscillator circuit having a plurality of stages. Each stage has a logic gate substantially identical to the logic gates of the reference ring oscillator circuit and electrically connecting to a respective at least one second independent voltage source. Each stage also has a FET load driven by the logic gate and electrically connecting to a third independent voltage source. A measured difference in capacitance between the reference ring oscillator circuit per stage and the at least one additional ring oscillator circuit per stage comprises a gate capacitance of a FET load.

Abstract: According to one exemplary embodiment, a frequency synthesizer module includes a loop filter, where the loop filter includes a capacitor having a first terminal and a second terminal. The frequency synthesizer module further includes a loop filter calibration module coupled to the capacitor in the loop filter. The loop filter calibration module causes an initial capacitance between the first terminal and the second terminal of the capacitor to increase to a target capacitance when the loop filter is in a calibration mode. The target capacitance can causes in increase in control of a bandwidth of the loop filter and a reduction in percent error of a unity gain bandwidth of the loop filter. The loop filter further includes a switched capacitor array configured to cause the initial capacitance to increase to the target capacitance in response to a digital feedback signal provided by the loop filter calibration module.

Abstract: An apparatus that minimizes phase error and jitter in a phase-locked loop. The apparatus includes a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider, which are coupled together to form a phase-locked loop. The charge pump within the phase-locked loop contains a pull-up network and a pull-down network which are coupled to each other, and a current compensation device. If the pull-up network and the pull-down network are both conducting, the current compensation device adjusts currents flowing through the pull-up network and through the pull-down network such that the currents are substantially equal. This ensures that very little current flows into the loop filter, thereby substantially minimizing a build-up of charge on a capacitor in the loop filter, which can cause phase error and jitter in the phase-locked loop.