Abstract: A clock oscillator system for use in providing the switching regulator duty cycle control in a fixed frequency (no cycle skipping) operation is provided. In one embodiment, the circuit according to the invention uses an analog feedback loop to extend the switch ON time of the clock cycle by controlling the oscillator charging current and, thereby, increase the duty cycle. Preferably, this circuit can achieve very high switching duty cycle and/or very low switching duty cycle in a PWM switching regulator operated in very low drop-out operation when very high duty cycle is required or in other conditions when very low duty cycle is required.

Abstract: Embodiments of High-Power Millimeter-Wave Oscillators are generally described herein. Other embodiments may be described and claimed. In some embodiments, the oscillator includes a polarized partial reflector to at least partially reflect back signals to a reflection array amplifier to help induce oscillation by individual sub-array amplifier elements of the reflection array amplifier. In some other embodiments, the oscillator includes a phase-graded polarization-sensitive reflection plate to at least partially reflect back signals to the reflection array amplifier to help induce an oscillation by the sub-array amplifier elements. In some embodiments, the oscillator includes a reflector and a phase-graded polarized reflection-transmission plate to at least partially pass through signals to the reflector for reflection back to the reflection array amplifier to help induce an oscillation by the sub-array amplifier elements.

Abstract: The invention is directed to an oscillator circuit in which a frequency-determining resonant circuit includes an inductive element, a first capacitive element and at least one second capacitive element which is connected in series with the first capacitive element. A node is provided between the first capacitive element and at least one second capacitive element. The oscillator circuit contains a damping reduction amplifier which is arranged in parallel with the frequency-determining resonant circuit. In addition, the oscillator circuit has a first tuneable capacitive element, which is connected in parallel with the first capacitive element of the resonant circuit and has a connection connected to the node.

Abstract: A phase-locked loop (PLL) circuit includes a power-on-reset (POR) to reset a digital block and set an initial input voltage value VCTRL of voltage-controlled oscillator (VCO). An input divider and a feedback divider are provided to set the frequency ratio of output to input and to raise the resolution of the output frequency. First and second phase frequency detectors are used to measure the phase difference between the two input signals and generate a pulse corresponding to the phase difference. First and second reducing dividers are inserted before the first and second phase frequency detectors to decrease the input frequency of the respective phase frequency detector and keep the ratio of the input frequency and natural frequency (Wn) as a constant. A lock-state detector is used to detect whether the PLL is locked or unlocked. A charge pump is used to provide charge signals corresponding to the pulse.

Abstract: When a power supply is turned on, an NPN transistor is disconnected, a first transmission gate is conducted, a second transmission gate is disconnected, and a power-supply voltage is applied to a control input terminal of a voltage controlled oscillation circuit via the first transmission gate. After oscillation of a quartz resonator is stabilized, the NPN transistor is switched to the conducted state by a control signal applied to a general purpose terminal so that the first transmission gate is switched to the disconnected state, and the second transmission gate is switched to the conducted state. Then, a voltage of the voltage control terminal is applied to the control input terminal of the voltage controlled oscillation circuit via the second transmission gate.

Abstract: The present invention pertains to an oscillator arrangement for carrying out a frequency modulation process, wherein an oscillator (1) with automatic amplitude control (5, 6, 7) is provided. The shift keying is not realized with reconnectable capacitances in the oscillator (1) that determine its oscillator frequency, but rather by suitably influencing (6) the feed current of the oscillator in dependence on the modulation signal (FSK), namely with the aid of the amplitude control (5, 6, 7). Undesirable charge injections do not occur in the proposed oscillator arrangement because reconnectable capacitances are no longer required for achieving the desired frequency deviation.

Abstract: A method for synthesizing frequencies with a low-jitter an all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, wherein the electronic circuit comprises a digital phase-frequency detector (DPFD) operatively connected to a digital loop filter (DLF), wherein the DPFD adapted to receive a reference signal and a feedback signal; compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between the reference and feedback signals; and provide a DPFD output comprising a multi-bit output; wherein the DLF is adapted to receive and filter the DPFD output and provide a DLF output, and wherein the DLF output is updated at each reference period.

Abstract: An oscillator comprising an active device having first, second and third terminals, a plurality of micro-stripline resonators coupled together to form a coupled-resonator network, the coupled-resonator network being coupled to the second terminal of the active device and a tuning network coupled to the coupled-resonator network, the tuning network being operable to adjust the coupling between at least two of the resonators that form the coupled resonator network.

Abstract: A method and circuit for performing switching in a frequency timing generator is described. The method includes detecting a request for a new value for a feedback counter or an reference counter, upon which a loading operation is synchronized for the appropriate counter. A time-out order of the feedback counter and the reference counter is determined. Where no time-out order difference is detected therein, a state machine status word function is completed. Where a time-out order difference is detected therein, it is determined which of the reference counter and the feedback counter times out first. Where the reference counter times out first, a constant charge pump current is delivered to a loop filter associated with a phase locked loop to achieve an upward frequency direction. Where the feedback counter times out first, a constant charge pump current is delivered to the loop filter to achieve a downward frequency direction.

Abstract: A current controlled, phase locked loop device includes a phase detector configured to compare a reference frequency to an output frequency of a current controlled oscillator (ICO), a charge pump coupled to the phase detector and a low pass filter coupled to the charge pump. A voltage to current (V to I) converter is coupled to the low pass filter, providing an output current for integral control of the ICO. A control circuit is coupled to the ICO, and receives increment and decrement outputs of the phase detector, wherein the control circuit is configured to provide proportional control of the ICO through an amount of bias current applied thereto.

Abstract: Circuits and methods for compensating a variable oscillator for process and/or operational variations. The circuit generally comprises (a) a replica oscillator, (b) a counter configured to count pulses of the replica oscillator and to produce a count signal, and (c) a compensation circuit configured to provide an adjustment signal to the variable oscillator in accordance with the count signal. The method generally comprises the steps of (a) counting the number of pulses of a replica oscillator signal, and (b) providing an adjustment signal to the variable oscillator in accordance with the number of pulses counted. The present invention advantageously provides a largely digital method to compensate a variable oscillator for process, voltage, and temperature variations.

Abstract: A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.

Abstract: A micro-oscillator is provided. In an example, the micro-oscillator applied to a signal filter and the like, ground capacitance thereof is reduced to control the loss of signal output. An oscillator element having a beam facing lower electrodes and to be electrostatically driven is formed on a substrate, and a wire width W1 of a DC bias feeder wire connected to the beam is formed to be narrower than a width of the beam.

Abstract: There are provided relaxation oscillators and methods for controlling the same. A relaxation oscillator includes a load device, a switching device, a fine-tuning varactor, and a current source. The load device is configured to provide a variable oscillator output based on a variable input reference voltage. The switching device is connected in signal communication with the load device and is configured to become active and inactive based on the variable oscillator output. The fine-tuning varactor is connected in signal communication with the switching device and is configured to provide fine-tuning of the variable oscillator output when the switching device is active. The current source is connected in signal communication with the switching device and is configured to provide coarse-tuning of the variable oscillator output when the switching device is active.

Abstract: A lead wire led-out type crystal oscillator of constant temperature type for high stability is disclosed, which includes a heat supply body that supplies heat to a crystal resonator from which a plurality of lead wires are led out, to maintain the temperature constant. The heat supply body includes a heat conducting plate which has through-holes for the lead wires and is mounted on the circuit board, and which faces, and is directly thermally joined to, the crystal resonator and a chip resistor for heating which is mounted on the circuit board adjacent to the heat conducting plate, and is thermally joined to the heat conducting plate.

Abstract: An apparatus and method for providing a stable gain over wide frequency range in a VCO are presented. A VCO uses a waveform generator along with a bias generator having a frequency select input. The frequency select input is used to adjust the amount of output current and/or gain of the bias generator. The output current of the bias generator determines the frequency of the output of the waveform generator. Multiple bias and waveform generators may be used to expand the frequency range of the VCO. A PLL may be programmed for a variety of output frequencies by using the frequency select input of the VCO.

Abstract: A method and apparatus for providing a radiation hardened Phase Locked Loop (PLL) are presented. The radiation hardened PLL includes an adjustable bandwidth loop filter. The adjustable filter modifies an unfiltered voltage control signal and provides a stable voltage control signal to a Voltage Controlled Oscillator (VCO) during detected radiation induced transient events. The adjustable filter filters out radiation effects by decreasing its bandwidth when a radiation event is detected.

Abstract: To provide dual loop PLLs capable of reducing the lock-up time in the initial start-up, and multiplication clock generators contributing to reduction of the power dissipation. The dual loop PLL comprises a dual loop PLL having a phase comparison loop having a phase comparator 1 for comparing phases, and a frequency comparison loop having a frequency comparator 7 for comparing frequencies, wherein the frequency comparator 7 carries out frequency comparison using an input signal inputted from a calibration clock line CLcal 18, the input signal being different from a reference clock signal inputted from an external reference clock line CLex 11, the reference clock signal being used for a phase comparator 1. Moreover, multiplication clock generators are configured using the dual loop PLL.

Abstract: An improved system and method for determining the lock condition of a Phase Locked Loop (PLL) is described. The lock detect circuit generates a fast lock detect signal that may be used to detect a transient loss of lock. The lock detect circuit may also include a phase alignment detect circuit to detect a misalignment in the phase of a reference clock and a feedback clock. Additionally, the lock detect circuit may include a reference clock detect circuit to detect if the reference clock signal is detected. Output signals from all of the above circuits may be communicated to a logic circuit in order to create an enhanced lock detect signal. An extended lock detect signal may also be communicated to the logic circuit.

Abstract: In a device for detecting the temperature of an oscillator crystal 2, arranged on a carrier, in particular in a mobile radio apparatus, the detected temperature should be as exact as possible a replica of the temperature to which the oscillator crystal 2 is subjected. For this purpose, a temperature sensor 7 is arranged on the carrier 1 in such a way that it is subjected to the same ambient temperature as the oscillator crystal 2 or the oscillator-crystal housing 2?. The temperature sensor 7 and the oscillator crystal 2 are located so as to be electrically parallel.