Abstract: A transmission and reception system includes a transmission circuit and a reception circuit. The transmission circuit is configured to generate a transmission signal based on an input signal. The reception circuit is configured to generate an output signal based on the transmission signal. The transmission circuit is configured to provide a duty cycle offset which is complementary with a duty cycle offset of the reception circuit.

Abstract: The present techniques relate to voltage droop detection and there is disclosed circuitry for detecting a voltage droop event, the circuitry configured to: receive a clock signal from a clock distribution network; obtain, from a storage, a first predetermined value, a second predetermined value and a predetermined threshold count; obtain one or more measurement values associated with a system voltage; when a first measurement value of the one or more measurement values reaches the first predetermined value, initiate a count of clock cycles until a subsequent measurement value of the one or more measurement values reaches the second predetermined value, the second predetermined value being different from the first predetermined value; and when the count of clock cycles is lower than the predetermined threshold count, cause a control entity to take mitigation action.

Abstract: A cross-coupled latch charge pump is provided, including a first inverter, a second inverter, and an output of the first inverter is connected to an input of the second inverter and an output of the second inverter is connected to an input of the first inverter. The first supply terminals of both the first and second inverter are connected to an output capacitor and second supply terminals for both the first and second inverter are connected to a reference voltage, a first fly capacitor, a second fly capacitor, and a first plate of the second fly capacitor is arranged for receiving a second clock signal, and a second plate of the second fly capacitor is connected to the input of the second inverter. The cross-coupled latch charge pump includes a transistor connected between the reference voltage and the second supply terminals.

Abstract: According to one embodiment, a charge pump circuit includes: a current source; a first current mirror including an input terminal connected to the current source; a second current mirror including an input terminal connected to an output terminal of the first current mirror; a third current mirror including an input terminal connected to a first output terminal of the second current mirror; a first switch including a first end connected to a second output terminal of the second current mirror via a first node, and including a second end; and an output terminal connected to an output terminal of the third current mirror and the second end of the first switch via a second node.

Abstract: A clock distribution system includes a clock mesh structure which has first metal patterns extending along a first axis, second metal patterns extending along a second axis, third metal patterns extending along a third axis. The first metal patterns, second metal patterns, and third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis. The first metal patterns include a main first metal pattern, and other first metal patterns. The second metal patterns include a main second metal pattern, and other second metal patterns. The third metal patterns include a main third metal pattern, and other third metal patterns. The main third metal pattern overlaps the main first metal pattern and the main second metal pattern, without overlapping the other first metal patterns or the other second metal patterns.

Abstract: The disclosure relates to an electronic circuit to verify the integrity of a switch. The circuit comprises a voltage comparator and decoupling switch. The decoupling switch configured receive the driving signal having a first logic value to enable the monitoring of the comparison voltage and is configured to receive the monitoring enable signal having a first logic value to command the opening of the decoupling switch. The electronic circuit is configured to generate the output monitoring signal having a first logic value in an event that the switch is an open circuit and having a second logic value in an event that the switch is a short circuit.

Abstract: A regulator circuit and driver including the regulator circuit use a variable-resistance element, such as a transistor, to limit the current in the circuit when the current is above a defined current threshold. The circuit may be comprised of a first amplifier circuit that senses a current in the circuit and generates a voltage signal in proportion thereto. The circuit also includes a mechanism for controlling a voltage applied to the first circuit element to limit the current flow. That may be a digital computing device that outputs a control voltage that causes the variable-resistance element to stop current flow for some defined period of time around current peaks.

Abstract: A clock output device includes a noise detector circuit and a clock buffer circuit. The noise detector circuit is configured to be enabled according to a request signal to determine whether a reference clock signal is a noise according to at least one of a common-mode level or a frequency of the reference clock signal and generate an enable signal. The clock buffer circuit is configured to be enabled according to the enable signal to generate an output clock signal according to the reference clock signal.

Abstract: A delay locked loop (DLL) includes a phase detector having a first input, a second input, and an output, and a first delay path coupled between an input of the DLL and the first input of the phase detector, wherein the first delay path includes a first delay circuit. The first delay circuit includes first delay buffers coupled in series and load capacitors, wherein each of the load capacitors is coupled to an output of a respective one of the first delay buffers. The DLL also includes a second delay path coupled between the input of the DLL and the second input of the phase detector, wherein the second delay path includes a one-cycle delay circuit and a second delay circuit coupled in series. The DLL also includes a control circuit coupled to the output of the phase detector, the first delay circuit, and the second delay circuit.

Abstract: A capacitive coupling isolation device and a receiving circuit are provided. The capacitive coupling isolation device includes an external coupling capacitor and the receiving circuit. The external coupling capacitor is electrically connected to a transmitting circuit and the receiving circuit. The receiving circuit includes a protection circuit architecture, which includes an input bonding pad structure and a filter resistor. The input bonding pad structure is formed by alternatively disposing patterned metal layers and dielectric layers, and the input bonding pad structure includes a pad capacitor and a filter capacitor. The pad capacitor is electrically connected to the external coupling capacitor and a filter capacitor. The filter capacitor and the filter resistor are both electrically connected to the pad capacitor and a ground end. The filter capacitor and filter resistor form a low-pass filter. The external coupling capacitor is a built-in package capacitor.

Abstract: A storage device includes an array of latching units and a plurality of inter-unit transmission switches. Each pair of two adjacent latching units is coupled together through an inter-unit transmission switch. Each latching unit includes a first inverter and a first transmission switch serially connected between a first bit node and a second bit node, and a second inverter and a second transmission switch serially connected between the second bit node and the first bit node. The first inverter has an input configured to receive a voltage from the first bit node either directly or through the first transmission switch. The second inverter has an input configured to receive a voltage from the second bit node either directly or through the second transmission switch.

Abstract: The demodulation circuit includes a waveform regulator, a first counter, a second counter, and an SR latch. The waveform regulator generates a regulated modulation signal according to a pair of differential isolated modulation signals, which is generated according to a modulation of an input data signal with a carrier clock signal. The first counter counts cycles of the regulated modulation signal so as to generate a set signal. The second counter counts cycles of a reference clock signal so as to generate a reset signal. The SR latch includes a set terminal for receiving the set signal, a reset terminal for receiving the reset signal, and an output terminal for outputting a demodulated output signal. The SR latch is triggered by the set signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.

Abstract: A digital duty cycle corrector circuit is provided. The duty cycle corrector circuit includes a control circuit having a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node. A single to differential circuit is connected to the control circuit at the second node. The single to differential circuit generates a first output clock and a second output clock from the duty adjusted output clock. A feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor.

Abstract: A Power-on Reset (POR) system includes: an SR latch circuit, powered by a supply voltage, for generating a POR signal according to the supply voltage and an enable signal; and at least one operating circuit, powered by the supply voltage. At least one state circuit in the operating circuit is reset by the POR signal. When the supply voltage starts up, an output terminal of the SR latch circuit has a predetermined state, such that after the supply voltage starts up and before the enable signal is enabled for a first time, the POR signal is in a reset state to reset the at least one state circuit in the operating circuit. After the supply voltage starts up and the enable signal is enabled for the first time, the POR signal turns to a non-reset state, and the operating circuit is enabled to operate according to the enable signal.

Abstract: A method for quadrature phase shifted clock generation with duty cycle correction includes A reference clock is delayed with a delay circuit to generate a delayed clock, wherein a delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock comprise a plurality of states comprising a first state and a second state. A first edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. A second edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. The control value is driven to the first edge value during the second state of the delayed clock and to the second edge value during the first state of the delayed clock.

Abstract: A receiver circuit is configured to generate, based on a clock signal, a first output signal by differentially amplifying an input signal and a reference voltage and to generate, based on a complementary clock signal, a second output signal by differentially amplifying the input signal and the reference voltage. The receiver circuit is configured to generate a first delay output signal and a second delay output signal by delaying the first output signal and the second output signal. The receiver circuit is configured to variably delay the first output signal based on the first output signal and the reference voltage and to variably delay the second output signal based on the second output signal and the reference voltage.

Abstract: Provided is a lamp system with improved visibility, and more particularly, to a lamp system positioned on a vehicle, the system including: a first lamp module generating a low beam, and outputting the low beam to the outside of the vehicle; a second lamp module generating light of a predetermined symbol, and outputting light to the outside of the vehicle; a sensor unit including at least one of an advanced driver assistance system (ADAS) sensor or an illumination sensor, and outputting external situation information; and a control unit receiving the output of the sensor unit, and controlling brightness of the second lamp module.

Abstract: An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.

Abstract: A power switch comprising: a cascode having a normally ON transistor connected in series with a normally OFF transistor at a cascode node; a safety switch between a gate of the normally ON transistor and a first ground common to the cascode and the switch; and a controller comprising: a controller power supply having a power supply output connected to the cascode node at which output the controller power supply provides a voltage relative to a second ground that is floating relative to the first ground; a first controller output connected to the gate of the normally ON transistor at which the controller generates a first voltage relative to the second ground; wherein the controller power supply is connected to the safety switch and voltage provided by the controller power supply is coupled to and operates to maintain the safety switch OFF and nonconducting and in the absence of the voltage the safety switch is turned ON and conducting.

Abstract: An example apparatus includes clock divider circuitry configured to divide a system clock by a pre-scaler input to generate a divided clock; counter circuitry configured to increment a system count based on the divided clock; comparison circuitry configured to determine a count difference between the system count and a real-time clock count; and controller circuitry configured to modify the pre-scaler input based on a comparison of the count difference to a threshold value.