Abstract: A current control unit 10 of a phase interpolation circuit 1 includes M slice circuits 60B0 to 60BM-1 having a common configuration. Each slice circuit 60Bm includes a selector 61, a PMOS transistor 62, an NMOS transistor 63, a PMOS transistor 64, an NMOS transistor 65, a first standby voltage set circuit 70, and a second standby voltage set circuit 80. The first standby voltage set circuit 70 has a configuration connecting the first node N1 and the voltage source via a switch the on/off of which is set according to the output signal from the selector 61, and sets the first node N1 to a standby voltage by supplementarily charging and discharging the parasitic capacitance of the first node N1 when the switch is in the on state.

Abstract: In accordance with a first aspect of the present disclosure, a networkable lighting device is provided, comprising: an ultra-wideband (UWB) communication unit; a mode controller operatively coupled to the UWB communication unit; wherein the mode controller is configured to cause the UWB communication unit to operate in a radar mode; and wherein the UWB communication unit is configured to, when operating in said radar mode, detect at least one living object present within a predefined area around or near the lighting device. In accordance with a second aspect of the present disclosure, a corresponding method of operating a networkable lighting device is conceived. In accordance with a third aspect of the present disclosure, a computer program is provided for carrying out said method.

Abstract: A driver circuit for controlling a high-power switch. The driver circuit comprises a flyback converter and a driving stage. The flyback converter includes a controller that configured to: receive a PWM control signal, which is for controlling the high-power switch; receive a feedback voltage signal, representative of a measured voltage of a positive output rail or the negative output rail of the flyback converter; and provide a primary-side switch control signal that comprises a bursts of pulses for operating the primary switch, wherein the controller is configured to start a burst of pulses in response to an edge of the PWM control signal, and stop the burst of pulses in response to the feedback voltage crossing a threshold. The driving stage is connected between the positive output rail and the negative output rail. The driving circuit is configured to provide a high-power switch control signal for controlling the state of the high-power switch based on the PWM control signal.

Abstract: A transmission circuit includes a plurality of driving units coupled with an input/output pad. The transmission circuit performs a data transmission operation by selecting at least one main driving unit corresponding to a predetermined driving strength from among the plurality of driving units and performs an equalization operation by selecting at least one auxiliary driving unit from among remaining driving units excluding the main driving unit.

Abstract: A first current source is configured to generate a first current switchable between a first current amount and a second current amount less than the first current amount. A first current mirror circuit has an input node to which the first current source is connected and is configured to fold and supply the first current to a gate of a power transistor. An on-fixing switch is connected between the gate of the power transistor and a high-level line in which a high voltage equivalent to a high level of a gate voltage of the power transistor is generated. A control circuit is configured to control the on-fixing switch and the first current source.

Abstract: A semiconductor integrated circuit device includes an internal circuit receiving a first power voltage including a first voltage level as a power source of the internal circuit and outputting a data signal including the first voltage level. The device further includes an interface circuit connected between the internal circuit and an output pad, the interface circuit including a plurality of low voltage transistors driven at the first power voltage. The interface circuit receives a second power voltage greater than the first power voltage as a power source of the interface circuit and the data signal, processes the data signal at least one control bias for controlling internal voltages of the low voltage transistors of no more than a maximum operating voltage, and provides the output pad with an output data signal.

Abstract: Four-switch buck boost power stages with reduced overshoot conditions at an output node are presented. Based on a detected condition for a decrease in a quantity of the active load elements, the method includes enabling an active discharge circuit coupled to an output node of a power stage before the quantity of the active load elements is decreased. Based on a detected condition for an increase in the quantity of the active load elements, the method includes activating the load elements and applying a restricted gain to the voltage conversion circuit.

Abstract: A computing system includes a communication system comprising a glitch filter circuitry disposed in an integrated circuit (IC) device configured to receive an input signal and provide a glitch filter output signal based on the input signal. The glitch filter circuitry includes a control path circuitry configured to receive the input signal and generate a control signal based on detecting a glitch within the input signal, the control path circuitry including a configurable resistor capacitor (RC) filter circuitry configured to deliver a configurable RC filter circuitry output signal based on one or more selection signals. The control signal is based on the configurable RC filter circuitry output signal, and a data path circuitry configured to receive the control signal and mitigate glitches within the input signal based on the control signal.

Abstract: A method includes generating a shaped gate signal using a gate voltage generator and providing the shaped gate signal to a gate of an active component of a radio frequency (RF) chain in a time delay-based array. The method also includes amplifying noise with a changing gain based on the shaped gate signal using the active component and generating shaped noise data based on the amplified noise using the RF chain. The method further includes measuring a path length for the RF chain based on an arrival time for the shaped noise data and calculating a time delay for the RF chain based on the path length to calibrate the array.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques to generate signals for clock spur attenuation. An example apparatus generally includes: one or more circuits coupled between a voltage rail and a reference potential node, wherein the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delay signal; and signal generation circuitry coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delay signal.

Abstract: A transmission and reception system includes a transmission circuit and a reception circuit. The transmission circuit is configured to generate a transmission signal based on an input signal. The reception circuit is configured to generate an output signal based on the transmission signal. The transmission circuit is configured to provide a duty cycle offset which is complementary with a duty cycle offset of the reception circuit.

Abstract: The present techniques relate to voltage droop detection and there is disclosed circuitry for detecting a voltage droop event, the circuitry configured to: receive a clock signal from a clock distribution network; obtain, from a storage, a first predetermined value, a second predetermined value and a predetermined threshold count; obtain one or more measurement values associated with a system voltage; when a first measurement value of the one or more measurement values reaches the first predetermined value, initiate a count of clock cycles until a subsequent measurement value of the one or more measurement values reaches the second predetermined value, the second predetermined value being different from the first predetermined value; and when the count of clock cycles is lower than the predetermined threshold count, cause a control entity to take mitigation action.

Abstract: A cross-coupled latch charge pump is provided, including a first inverter, a second inverter, and an output of the first inverter is connected to an input of the second inverter and an output of the second inverter is connected to an input of the first inverter. The first supply terminals of both the first and second inverter are connected to an output capacitor and second supply terminals for both the first and second inverter are connected to a reference voltage, a first fly capacitor, a second fly capacitor, and a first plate of the second fly capacitor is arranged for receiving a second clock signal, and a second plate of the second fly capacitor is connected to the input of the second inverter. The cross-coupled latch charge pump includes a transistor connected between the reference voltage and the second supply terminals.

Abstract: According to one embodiment, a charge pump circuit includes: a current source; a first current mirror including an input terminal connected to the current source; a second current mirror including an input terminal connected to an output terminal of the first current mirror; a third current mirror including an input terminal connected to a first output terminal of the second current mirror; a first switch including a first end connected to a second output terminal of the second current mirror via a first node, and including a second end; and an output terminal connected to an output terminal of the third current mirror and the second end of the first switch via a second node.

Abstract: A clock distribution system includes a clock mesh structure which has first metal patterns extending along a first axis, second metal patterns extending along a second axis, third metal patterns extending along a third axis. The first metal patterns, second metal patterns, and third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis. The first metal patterns include a main first metal pattern, and other first metal patterns. The second metal patterns include a main second metal pattern, and other second metal patterns. The third metal patterns include a main third metal pattern, and other third metal patterns. The main third metal pattern overlaps the main first metal pattern and the main second metal pattern, without overlapping the other first metal patterns or the other second metal patterns.

Abstract: The disclosure relates to an electronic circuit to verify the integrity of a switch. The circuit comprises a voltage comparator and decoupling switch. The decoupling switch configured receive the driving signal having a first logic value to enable the monitoring of the comparison voltage and is configured to receive the monitoring enable signal having a first logic value to command the opening of the decoupling switch. The electronic circuit is configured to generate the output monitoring signal having a first logic value in an event that the switch is an open circuit and having a second logic value in an event that the switch is a short circuit.

Abstract: A regulator circuit and driver including the regulator circuit use a variable-resistance element, such as a transistor, to limit the current in the circuit when the current is above a defined current threshold. The circuit may be comprised of a first amplifier circuit that senses a current in the circuit and generates a voltage signal in proportion thereto. The circuit also includes a mechanism for controlling a voltage applied to the first circuit element to limit the current flow. That may be a digital computing device that outputs a control voltage that causes the variable-resistance element to stop current flow for some defined period of time around current peaks.

Abstract: A clock output device includes a noise detector circuit and a clock buffer circuit. The noise detector circuit is configured to be enabled according to a request signal to determine whether a reference clock signal is a noise according to at least one of a common-mode level or a frequency of the reference clock signal and generate an enable signal. The clock buffer circuit is configured to be enabled according to the enable signal to generate an output clock signal according to the reference clock signal.

Abstract: A delay locked loop (DLL) includes a phase detector having a first input, a second input, and an output, and a first delay path coupled between an input of the DLL and the first input of the phase detector, wherein the first delay path includes a first delay circuit. The first delay circuit includes first delay buffers coupled in series and load capacitors, wherein each of the load capacitors is coupled to an output of a respective one of the first delay buffers. The DLL also includes a second delay path coupled between the input of the DLL and the second input of the phase detector, wherein the second delay path includes a one-cycle delay circuit and a second delay circuit coupled in series. The DLL also includes a control circuit coupled to the output of the phase detector, the first delay circuit, and the second delay circuit.

Abstract: A capacitive coupling isolation device and a receiving circuit are provided. The capacitive coupling isolation device includes an external coupling capacitor and the receiving circuit. The external coupling capacitor is electrically connected to a transmitting circuit and the receiving circuit. The receiving circuit includes a protection circuit architecture, which includes an input bonding pad structure and a filter resistor. The input bonding pad structure is formed by alternatively disposing patterned metal layers and dielectric layers, and the input bonding pad structure includes a pad capacitor and a filter capacitor. The pad capacitor is electrically connected to the external coupling capacitor and a filter capacitor. The filter capacitor and the filter resistor are both electrically connected to the pad capacitor and a ground end. The filter capacitor and filter resistor form a low-pass filter. The external coupling capacitor is a built-in package capacitor.