Patents Examined by Ryan Jager
  • Patent number: 10804896
    Abstract: The invention relates to a proximity magnetic induction switch control chip and a control method thereof. A proximity magnetic induction switch control chip includes a voltage regulator module, a control module, an output type detection module, a first controllable switch and a second controllable switch. An output type detection module detects proximity magnets. An output type detection module detects a load connected between a voltage input and a signal output of a proximity magnetic induction switch control chip or a load connected between a signal output and a ground terminal. The detection result is transmitted to the control module. The control module controls the first controllable switch or the second controllable switch to actuate the load according to the detection result.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 13, 2020
    Assignee: SHENZHEN MOJAY SEMICONDUCTOR LIMITED
    Inventor: Jian Wang
  • Patent number: 10804892
    Abstract: A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: October 13, 2020
    Assignee: pSemi Corporation
    Inventors: Alexander Dribinsky, Tae Youn Kim, Dylan J. Kelly, Christopher N. Brindle
  • Patent number: 10782727
    Abstract: Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: September 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Angelo William Pereira, Pinar Korkmaz, Sujan Kundapur Manohar
  • Patent number: 10778214
    Abstract: A circuit structure is electrically connected to a power source. The circuit structure includes a first circuit module and a second circuit module. The first circuit module includes a first module power switch and a plurality of circuits. The first module power switch is electrically connected to the power source. The first circuit module has a first module current. The second circuit module includes a second module power switch and a plurality of circuits. The second power switch is electrically connected to the power source. The second circuit module has a second module current. A turn-on order of the first module power switch and the second power switch is determined based on the first module current and the second module current.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 15, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chien-Cheng Liu, Yun-Ru Wu, Yun-Chih Chang, Shu-Yi Kao
  • Patent number: 10775832
    Abstract: A clock determination apparatus includes a signal wire and a clock determiner. A clock signal is input to the signal wire. A period made up of cycles corresponding to a predetermined number of cycles of the clock signal is referred to as a unit period. The clock determiner includes circuitry configured to perform determination processing whether the clock signal is a random clock signal including a cycle changing substantially irregularly as time proceeds or a regular clock signal including substantially a constant cycle based on a comparison between waveforms of the clock signals in a plurality of unit periods.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: September 15, 2020
    Assignee: MEGACHIPS CORPORATION
    Inventor: Mitsuru Tamura
  • Patent number: 10776550
    Abstract: An integrated circuit includes a path logic and a timing fixing circuit. The path logic is coupled between an output pin of a first circuit and an input pin of a second circuit. The timing fixing circuit has an input pin coupled to the path logic, and is used to adjust a propagation delay of the path logic. The timing fixing circuit introduces no short-circuit current under normal operation.
    Type: Grant
    Filed: April 14, 2019
    Date of Patent: September 15, 2020
    Assignee: MEDIATEK INC.
    Inventors: Yi-Feng Chen, Chun-Sung Su
  • Patent number: 10777142
    Abstract: The present disclosure discloses a gate drive output stage circuit, a gate driving unit, and a drive method. The gate drive output stage circuit includes: a first control sub-circuit configured to transmit a start signal of a compensation driving terminal to a first node; a second control sub-circuit configured to transmit a first clock signal of a first clock terminal to a control node when the first node is at an effective level; a first output sub-circuit configured to transmit a second clock signal of a second clock terminal to a first output terminal when the control node is at an effective level; and a second output sub-circuit configured to transmit a first power supply voltage signal of a first power supply voltage terminal to a second output terminal when the control node is at the effective level.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 15, 2020
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhidong Yuan, Can Yuan, Yongqian Li
  • Patent number: 10778034
    Abstract: A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: September 15, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ashish Khandelwal, Joseph M. Khayat, Yipeng Su, Robert A. Neidorff, Bharath B. Kannan
  • Patent number: 10770410
    Abstract: A system with circuit alteration detection can include a shield in at least one metal layer over an integrated circuit, and a detector coupled to the shield to detect a change in impedance characteristics of one or more shield lines of the shield due to physical alteration of the shield. The shield lines can be arranged in one or more metal layers and cover an area with shape arrangements such as parallel lines and serpentines. The detector can include one or more comparators to detect a difference in impedance of more than a tolerance value. An appropriate countermeasure response can be initiated upon detection of the difference in impedance.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: September 8, 2020
    Assignee: ARM LIMITED
    Inventors: Mikael Yves Marie Rien, Subbayya Chowdary Yanamadala
  • Patent number: 10771053
    Abstract: First and second switching regions include first and second gate electrodes respectively. Channel currents of the first and second switching regions are controlled according to electric charge amounts supplied by control signals input to the first and second gate electrodes respectively. The second switching region is connected in parallel with the first switching region. A control section outputs a first control signal for turning-on the first switching region to the first gate electrode and a second control signal for turning-on the second switching region to the second gate electrode. The control section stops outputting the second control signal after a first predetermined period elapses from a start of outputting the first and second control signals, and outputs the second control signal after a second predetermined period elapses from a stop of outputting the second control signal.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: September 8, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Keisuke Eguchi, Takahiro Inoue, Rei Yoneyama, Shiori Uota, Haruhiko Murakami
  • Patent number: 10763842
    Abstract: a radio frequency (RF) switching circuit, including: a conducting module, configured to conduct an RF signal; a gate control voltage generating module, configured to provide a gate control voltage for the conducting module to control the conducting module operating at ON-state or OFF-state; wherein the gate control voltage generating module further includes: a first resistance adaptive module, providing a first impedance in a first state for a series branch where the conducting module and the gate control voltage generation module locate, and a second impedance in a second state for the series branch where the conducting module and the gate control voltage generation module locate, wherein the first impedance is greater than the second impedance. FOM is improved comprehensively, and Ron, Coff, and a power breakdown performance are optimized, which further improves circuit performance and reduces cost.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 1, 2020
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Ruofan Dai
  • Patent number: 10763836
    Abstract: Disclosed is a measuring circuit for quantizing variations in the operating speed of a target circuit. The measuring circuit includes: a signal generator configured to generate a predetermined signal; an adjustable delay circuit configured to generate a first and second delay signals according to the predetermined signal respectively; a signal detector configured to detect the first and second delay signals respectively and thereby generate a first and second detection results respectively; and a calibrating circuit configured to enable a first and second numbers of delay units of the adjustable delay circuit according to the first and second detection results respectively so as to make each of the delays respectively caused by the first and second numbers of delay units be less than a delay threshold, in which the first and second numbers relate to the operating speed of the target circuit operating in the first and second conditions respectively.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: September 1, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Yi Kuo, Ying-Yen Chen, Wen-Hsuan Hsu
  • Patent number: 10763837
    Abstract: A reference oscillator for a transmitter and/or a receiver of electromagnetic signals. The reference oscillator is suitable for generating a modified reference signal alternating ON times and OFF times with a predefined duty cycle from a signal supplied by a reference resonator. The reference oscillator also includes an adjustment circuit suitable for adjusting the duty cycle of the modified reference signal according to at least one adjustment parameter dependent on a rank of at least one harmonic component of the modified reference signal so as to minimize at least one harmonic component of the modified reference signal. A frequency synthesizer and a radio frequency signal receiver can include such a reference oscillator.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 1, 2020
    Assignee: The Swatch Group Research and Development Ltd
    Inventor: Arnaud Casagrande
  • Patent number: 10763854
    Abstract: A semiconductor integrated circuit includes a level shifter formed in a portion of a high-voltage junction termination structure and an isolation region formed surrounding the periphery of the level shifter. The level shifter includes a p-type base region formed in an upper portion of a p? substrate, an n? source region formed contacting the base region, an n+ drift region formed contacting the base region, a drain region formed in an upper portion of the drift region, and a control electrode that controls the voltage of the base region. In a planar pattern, an effective channel width defined by the width of the base region in a portion that overlaps with the control electrode is greater than the width of the drain region as measured along the same direction as the effective channel width.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: September 1, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takahide Tanaka
  • Patent number: 10756714
    Abstract: Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device comprises multiple sub-circuits belonging to different clock domains. The clock distribution network comprises a clock source operable for providing a global clock signal, at least one programmable delay line associated with a certain sub-circuit operable for generating a local clock signal for said sub-circuit by delaying the global clock signal or a signal derived therefrom and a global skew control circuit for managing clock skew between the local clock signals. The global skew control circuit is operable for managing clock skew between at least some local clock signals by regularly adjusting the delay caused by at least one programmable delay line when in a deskewing operating mode, and disabling adjusting the delays of the programmable delay lines when in a locked operating mode.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andreas Arp, Fatih Cilek, Michael Koch, Matthias Ringe
  • Patent number: 10749523
    Abstract: A switch circuit includes: a switching device control circuit receiving a first voltage and a second voltage, a first Type-I switching device coupled to the switching device control circuit and a first control voltage, a first Type-II switch element coupled to the switch control circuit and the first Type-I switch element, and a second Type-II switch element coupled to the first Type-I switch element and the first Type-II switch element. When the second voltage is higher than the first voltage, the switch control circuit turns on the first Type-II switch element in order to turn off the second Type-II switch element; and when the second voltage is higher than the first voltage, the first Type-I switch element is off.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: August 18, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ya-Hsuan Sung, Leaf Chen
  • Patent number: 10739808
    Abstract: The reference voltage generator includes an output terminal, first to fourth resistors, first to fourth transistors, and a diode unit. The first transistor is coupled to the second transistor. The first resistor is coupled between the second transistor and a second reference voltage terminal. The first resistor is also coupled to the first transistor. One terminal of the diode unit is coupled to the output terminal, and the other terminal of the diode unit is coupled to the second and third resistors. The second and third resistors are also coupled to the first and second transistors, respectively. The third transistor is coupled between the fourth resistor and the second reference voltage terminal, and includes a control terminal coupled to the second transistor. The fourth transistor is coupled between a first reference voltage terminal and the diode unit. The fourth transistor is also coupled to the fourth resistor.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 11, 2020
    Assignee: RichWave Technology Corp.
    Inventor: Kuang-Lieh Wan
  • Patent number: 10741363
    Abstract: A radio frequency (RF) generator includes a RF power source configured to generate an output signal at an output frequency. The RF generator includes a frequency tuning module. The frequency tuning module generates a frequency control signal that controls the output frequency of the RF power source. The frequency control signal includes a frequency tuning signal component and a perturbation signal component. The perturbation signal varies an electrical parameter of the output signal. The frequency tuning signal is adjusted in accordance with a change in output signal in response to the perturbation signal.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: August 11, 2020
    Assignee: MKS Instruments, Inc.
    Inventors: Aaron M. Burry, Aaron T. Radomski, Aung Toe, Jesse N. Klein
  • Patent number: 10734976
    Abstract: A driving circuit for driving a power switch. The driving circuit and the power switch are collaboratively defined as an equivalent circuit. The equivalent circuit includes a first equivalent capacitor corresponding to an input capacitor of the power switch, an equivalent inductor, and a second equivalent capacitor corresponding to a parasitic parameter of at least one driving switch. In the charging procedure or the discharging of the first equivalent capacitor, a change amount of charges in the first equivalent capacitor while a voltage of the input capacitor is changed from a voltage corresponding to no inductor current to a set voltage is larger than or equal to a change amount of charges in the second equivalent capacitor while the voltage of the input capacitor is changed from the voltage corresponding to no inductor current to a steady voltage.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 4, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Peiqing Hu, Jianhong Zeng, Haoyi Ye
  • Patent number: 10734985
    Abstract: In certain aspects, a comparator includes a first inverter having an input, an output, and a voltage supply input, wherein the input of the first inverter and the output of the first inverter are coupled together, and the voltage supply input of the first inverter is configured to receive a first compare voltage. The comparator also includes a second inverter having an input, an output, and a voltage supply input, wherein the input of the second inverter is coupled to the output of the first inverter, and the voltage supply input of the second inverter is configured to receive a second compare voltage.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: August 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Byron Murphy, Glenn Murphy, Rajeev Jain