Abstract: A multi-stage negative charge pump, method and circuit. The circuit includes an input supplying a charge-pump reference voltage (VDDW) to the negative charge pump. A plurality of stages is connected in sequence and an output of a last stage provides a negative charge pump output voltage. Each stage, except the last stage, adds negative VDDW, and the last stage adds a negative fraction of VDDW. An oscillator clock drives each stage, except the last stage. A modulated oscillator clock drives the last stage by a repeating cycle of a modulated oscillator clock, which oscillates during a first time, and stops oscillating during a second time, to generate the negative fraction of VDDW. Durations of the first and second times are defined by an output voltage from a comparator comparing a reference voltage to a voltage from a voltage divider dividing a difference between the output voltage and an LDO voltage.

Abstract: A circuit includes an input node configured to receive a gate control signal for controlling a dual gate transistor arrangement, a first output node configured to be coupled to a first gate node of the dual gate transistor arrangement, a first switch coupled between the input node and the first output node, and a second output node configured to be coupled to a second gate node of the dual gate transistor arrangement and coupled to the input node. A control circuit is configured to, upon detecting that the gate control signal indicates a turn-off of the dual gate transistor arrangement, open the first switch for a first predefined time period, and close the first switch after the first predefined time period.

Abstract: Aspects of the subject disclosure may include, for example, first and second operational amplifiers; and a differential pair of NPN transistors in a feedback path of the TLA configured to convert an input current signal into an output voltage signal, where a first emitter of a first NPN transistor of the pair of NPN transistors is connected to an inverting input of the first operational amplifier, and where a second emitter of a second NPN transistor of the pair of NPN transistors is connected to a non-inverting input of the second operational amplifier. Other embodiments are disclosed.

Abstract: A switching circuit receives an input voltage and outputs an output voltage, and includes a first switched-capacitor circuit, a second switched-capacitor circuit, and a switch. The first switched-capacitor circuit is configured to receive the input voltage to generate an intermediate voltage. The second switched-capacitor circuit is coupled to the first switched-capacitor circuit and is configured to receive the intermediate voltage to generate the output voltage. One terminal of the switch receives the input voltage, and another terminal of the switch is coupled to the second switched-capacitor circuit.

Abstract: An integrated circuit (IC) chip includes a voltage supply circuit to provide a supply voltage. A droop recovery circuit is responsive to a droop event acting upon the supply voltage. The droop recovery circuit restores a clock signal from a droop-reduced frequency to a nominal operating frequency. The droop recovery circuit includes a ramp controller to increase the clock frequency from the droop-reduced frequency to the nominal operating frequency over a sloped-step frequency profile during a recovery timing interval corresponding to a timing interval representing a diminishing of the droop event.

Abstract: In a described example, a circuit includes a pulse generator having an input and an output and an oscillator having an output. The circuit also includes a logic circuit having a first input, a second input, and an output, the first input of the logic circuit coupled to the output of the pulse generator, and the second input of the logic circuit coupled to the output of the pulse generator. Additionally, the circuit includes an output circuit having a first input, a second input, a third input and an output, the second input of the output circuit coupled to the output of the logic circuit.

Abstract: In accordance with an embodiment, power module includes a module control terminal, a first module load terminal and a second module load terminal and at least one power switch comprising a plurality of switching devices coupled in parallel. Each switching device comprises a control terminal, a first load terminal and a second load terminal. The control terminals are coupled to the module control terminal via a plurality of control paths, the first load terminals are coupled to the first module load terminal via a plurality of first load paths, and the second load terminals are coupled to the second module load terminal via a plurality of second load paths. A control path, a first load path or a second load path has at least one electrical parameter respectively differing from the other control paths, other first load paths and other second load paths.

Abstract: A clock transmission circuit including a first inverter configured to inversion-drive a first transmission node in response to a first clock signal, among differential clock signals that are loaded onto a first reception node, a second inverter configured to inversion-drive a second transmission node in response to a second clock signal, among the differential clock signals that are loaded onto a second reception node, a first additional driver configured to additionally drive the first transmission node in response to the second clock signal that is loaded onto the second reception node, and a second additional driver configured to additionally drive the second transmission node in response to the first clock signal that is loaded onto the first reception node.

Abstract: A clock circuit comprising a voltage-controlled oscillator having an input coupled to an output of an amplifier, and an output, outputting an output clock signal. The clock circuit further comprises, a reference branch and a feedback branch, both comprising, a first switch coupled to an input via an inverter and a second switch coupled to the input. The branches also both comprise, a variable capacitor coupled to a reference potential and coupled to the first switch, and a variable resistor coupled to the first switch. Both branches comprise a supply voltage coupled to the variable resistor and an output node, wherein the second switch is coupled to the variable capacitor and coupled to a node. The reference branch input is an input clock signal and the output is a reference voltage, and the feedback branch input is an output clock signal and the output is a feedback voltage.

Abstract: A current control unit 10 of a phase interpolation circuit 1 includes M slice circuits 60B0 to 60BM-1 having a common configuration. Each slice circuit 60Bm includes a selector 61, a PMOS transistor 62, an NMOS transistor 63, a PMOS transistor 64, an NMOS transistor 65, a first standby voltage set circuit 70, and a second standby voltage set circuit 80. The first standby voltage set circuit 70 has a configuration connecting the first node N1 and the voltage source via a switch the on/off of which is set according to the output signal from the selector 61, and sets the first node N1 to a standby voltage by supplementarily charging and discharging the parasitic capacitance of the first node N1 when the switch is in the on state.

Abstract: In accordance with a first aspect of the present disclosure, a networkable lighting device is provided, comprising: an ultra-wideband (UWB) communication unit; a mode controller operatively coupled to the UWB communication unit; wherein the mode controller is configured to cause the UWB communication unit to operate in a radar mode; and wherein the UWB communication unit is configured to, when operating in said radar mode, detect at least one living object present within a predefined area around or near the lighting device. In accordance with a second aspect of the present disclosure, a corresponding method of operating a networkable lighting device is conceived. In accordance with a third aspect of the present disclosure, a computer program is provided for carrying out said method.

Abstract: A driver circuit for controlling a high-power switch. The driver circuit comprises a flyback converter and a driving stage. The flyback converter includes a controller that configured to: receive a PWM control signal, which is for controlling the high-power switch; receive a feedback voltage signal, representative of a measured voltage of a positive output rail or the negative output rail of the flyback converter; and provide a primary-side switch control signal that comprises a bursts of pulses for operating the primary switch, wherein the controller is configured to start a burst of pulses in response to an edge of the PWM control signal, and stop the burst of pulses in response to the feedback voltage crossing a threshold. The driving stage is connected between the positive output rail and the negative output rail. The driving circuit is configured to provide a high-power switch control signal for controlling the state of the high-power switch based on the PWM control signal.

Abstract: A transmission circuit includes a plurality of driving units coupled with an input/output pad. The transmission circuit performs a data transmission operation by selecting at least one main driving unit corresponding to a predetermined driving strength from among the plurality of driving units and performs an equalization operation by selecting at least one auxiliary driving unit from among remaining driving units excluding the main driving unit.

Abstract: A first current source is configured to generate a first current switchable between a first current amount and a second current amount less than the first current amount. A first current mirror circuit has an input node to which the first current source is connected and is configured to fold and supply the first current to a gate of a power transistor. An on-fixing switch is connected between the gate of the power transistor and a high-level line in which a high voltage equivalent to a high level of a gate voltage of the power transistor is generated. A control circuit is configured to control the on-fixing switch and the first current source.

Abstract: A semiconductor integrated circuit device includes an internal circuit receiving a first power voltage including a first voltage level as a power source of the internal circuit and outputting a data signal including the first voltage level. The device further includes an interface circuit connected between the internal circuit and an output pad, the interface circuit including a plurality of low voltage transistors driven at the first power voltage. The interface circuit receives a second power voltage greater than the first power voltage as a power source of the interface circuit and the data signal, processes the data signal at least one control bias for controlling internal voltages of the low voltage transistors of no more than a maximum operating voltage, and provides the output pad with an output data signal.

Abstract: Four-switch buck boost power stages with reduced overshoot conditions at an output node are presented. Based on a detected condition for a decrease in a quantity of the active load elements, the method includes enabling an active discharge circuit coupled to an output node of a power stage before the quantity of the active load elements is decreased. Based on a detected condition for an increase in the quantity of the active load elements, the method includes activating the load elements and applying a restricted gain to the voltage conversion circuit.

Abstract: A computing system includes a communication system comprising a glitch filter circuitry disposed in an integrated circuit (IC) device configured to receive an input signal and provide a glitch filter output signal based on the input signal. The glitch filter circuitry includes a control path circuitry configured to receive the input signal and generate a control signal based on detecting a glitch within the input signal, the control path circuitry including a configurable resistor capacitor (RC) filter circuitry configured to deliver a configurable RC filter circuitry output signal based on one or more selection signals. The control signal is based on the configurable RC filter circuitry output signal, and a data path circuitry configured to receive the control signal and mitigate glitches within the input signal based on the control signal.

Abstract: A method includes generating a shaped gate signal using a gate voltage generator and providing the shaped gate signal to a gate of an active component of a radio frequency (RF) chain in a time delay-based array. The method also includes amplifying noise with a changing gain based on the shaped gate signal using the active component and generating shaped noise data based on the amplified noise using the RF chain. The method further includes measuring a path length for the RF chain based on an arrival time for the shaped noise data and calculating a time delay for the RF chain based on the path length to calibrate the array.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques to generate signals for clock spur attenuation. An example apparatus generally includes: one or more circuits coupled between a voltage rail and a reference potential node, wherein the one or more circuits are configured to operate using a clock signal; a delay signal generator configured to receive the clock signal and apply a delay to the clock signal to generate a delay signal; and signal generation circuitry coupled between the voltage rail and the reference potential node and configured to generate a signal fluctuation on at least one of the voltage rail or the reference potential node based on the delay signal.

Abstract: A transmission and reception system includes a transmission circuit and a reception circuit. The transmission circuit is configured to generate a transmission signal based on an input signal. The reception circuit is configured to generate an output signal based on the transmission signal. The transmission circuit is configured to provide a duty cycle offset which is complementary with a duty cycle offset of the reception circuit.