Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

Abstract: An embodiment provides method for controlling lamp output within an array of lamps, including: receiving sensor data corresponding to one of a plurality of lamps within the array, wherein the sensor data comprises an irradiance value from at least one of: within a lamp sleeve and an irradiance value from outside a lamp sleeve; identifying, based the sensor data, a change in an output of the one of the plurality of lamps; sharing the sensor data with other of the plurality of lamps within the array; and adjusting, in response to the sharing, an output of at least one of the other of the plurality of lamps within the array, thereby compensating for the change in the output of one of the plurality of lamps. Other aspects are described and claimed.

Abstract: A lighting unit (102) is disclosed. The lighting unit comprises: one or more light sources (110), a memory (108), a communication unit (104) comprising a first communication module (104a) configured to communicate via a first wireless communication technology, and a second communication module (104b) configured to communicate via a second wireless communication technology, and a processor (106) configured to receive, via the first communication module (104a), a first lighting control command (122), store the first lighting control command (122) in the memory (108), receive, via the second communication module (104b), a second lighting control command (124), and control the one or more light sources (110) according to the first lighting control command (122) upon receiving the second lighting control command.

Abstract: Disclosed is a method and a control circuit. The method includes operating a buffer circuit in a first operating mode or a second operating mode. Operating the buffer circuit in the first operating mode includes buffering, by a first capacitor of the buffer circuit, power provided by a power source and received by a load. Operating the buffer circuit in the second operating mode includes connecting a second capacitor in series with the first capacitor to form a capacitor series circuit, supplying power to the load by the capacitor series circuit, and regulating a first voltage across the capacitor series circuit. Regulating the first voltage includes transferring charge from the first capacitor to the second capacitor.

Abstract: A system (1) for configuring a bridge (13) in a wireless lighting system (31), which has been commissioned, is configured to determine that a bridge has been added to the wireless lighting system. The wireless lighting system comprises a plurality of lighting devices (14-19). The system is further configured to obtain information relating to the plurality of lighting devices, analyze the information, and determine one or more groups of lighting devices based on the analysis. At least one of the one or more groups comprises multiple of the plurality of lighting devices. The system is further configured to configure the bridge with the determined one or more groups upon determining that the bridge has been added to the wireless lighting system.

Abstract: Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.

Abstract: A signal correction circuit and a server are provided. The circuit comprises: a first signal processing component receiving an input signal and positive power supply voltages and negative power supply voltages, generating a first control voltage, and outputting a first voltage, the first voltage being zero within a first time period; a second signal processing component generating a second control voltage according to the first control voltage, performing energy storage charging according to the second control voltage, controlling an energy storage charging voltage according to the second control voltage, and outputting a second voltage, and the second voltage being zero in the second time period; and an output component performing superposition processing on the first voltage and the second voltage to obtain an output signal.

Abstract: A controller (1) configured to control properties of light emitted from a light emitting device (4), the controller comprises a control device (2) and a processing unit (3). The control device (2) enables a user to select a color point of the light emitted from the light emitting device (4) in a color space of the light emitting device. The selection of the color point is done by the user providing a single input to the control device (2). The processing unit (3) being configured to change the color point of light emitted from the light emitting device based on the single input. The change of the color point is done along a meandering curve extending along the black body locus (BBL) in accordance with the received single input.

Abstract: Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.

Abstract: A first drive circuit is connected to a first end of a primary winding of a pulse transformer. A second drive circuit is connected to a second end of the primary winding of the pulse transformer. A voltage clamp unit clamps a voltage of a semiconductor element at a specified voltage when a voltage output from a secondary winding of the pulse transformer is negative. A current detection circuit detects current flowing through the semiconductor element and outputs a detection signal. A control circuit controls the first drive circuit and the second drive circuit based on the detection signal. A current limiting circuit imposes a limit on current flowing through the primary winding of the pulse transformer based on the detection signal.

Abstract: An LED matrix lighting device for illuminating a lighting pattern with even intensity. The LED matrix lighting device includes a plurality of LEDs, a collimating lens in front of each LED for collimating light of the LED, and a light refracting element in front of collimating lenses arranged to refract light of at least a first part of the LEDs with a different refraction angle than at least a second part of the LEDs. The disclosure further relates to a machine vision system, a method, and a computer program product.

Abstract: Systems and methods for supplying power at a medium voltage from an uninterruptible power supply (UPS) to a load without using a transformer are disclosed. The UPS includes an energy storage device, a single stage DC-DC converter or a two-stage DC-DC converter, and a multi-level inverter, each of which are electrically coupled to a common negative bus. The DC-DC converter may include two stages in a unidirectional or bidirectional configuration. One stage of the DC-DC converter uses a flying capacitor topology. The voltages across the capacitors of the flying capacitor topology are balanced and switching losses are minimized by fixed duty cycle operation. The DC-DC converter generates a high DC voltage from a low or high voltage energy storage device such as batteries and/or ultra-capacitors. The multi-level, neutral point, diode-clamped inverter converts the high DC voltage into a medium AC voltage using a space vector pulse width modulation (SVPWM) technique.

Abstract: A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.

Abstract: A method for clock switching includes propagating a first clock signal through a first clock path, propagating a second clock signal through a second clock path, generating a first delay control signal based on the first clock signal, and generating a second delay control signal based on the second clock signal. The method also includes, in a first mode, coupling the first clock path to a delay circuit and inputting the first delay control signal to a control input of the delay circuit. The method also includes, in a second mode, coupling the second clock path to the delay circuit and inputting the second delay control signal to the control input of the delay circuit.

Abstract: A clock distribution system includes a clock mesh structure which has a plurality of first metal patterns extending along a first axis, a plurality of second metal patterns extending along a second axis, a plurality of third metal patterns extending along a third axis. The plurality of first metal patterns, the plurality of second metal patterns, and the plurality of third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis.

Abstract: A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.

Abstract: The present disclosure provides a delay circuit and a semiconductor device. The delay circuit includes a delay unit and a linear voltage regulator unit; wherein, the delay unit includes an inverting unit and a power supply control unit, and the inverting unit includes an inverting unit and a power supply control unit. The inversion unit receives an input signal and delays the input signal, and the power supply control unit is used for providing a voltage to the inverting unit according to the power supply control signal; the linear voltage stabilization unit is coupled to the delay unit and outputting the power supply control signal according to a reference voltage. The voltage outputs the power control signal. The present disclosure can accurately control the delay time of the delay unit and improve the delay precision of the delay circuit.

Abstract: Embodiments of the disclosure provide a structure and related method to delay data signals through a data path using a lockup latch driven by the inverse of a clock signal. A structure according to the disclosure provides a launch pulse latch coupled to a capture pulse latch through a data path. The data path includes a combinational logic for processing signals within the data path. An edge of a clock signal drives the launch pulse latch and the capture pulse latch. A lockup latch is within the data path between the launch pulse latch and the capture pulse latch. An inverse of the clock signal drives the lockup latch.

Abstract: A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.

Abstract: A level shifter circuit of a driving device includes first and second pulse generators, first and second level shifters, and a determination circuit. The first pulse generator provides a first input signal according to a high-voltage signal. The first input signal includes a pulse signal having a first current level and a sustain signal having a second current level following the pulse signal. The first level shifter receives the first input signal to generate a first indication signal. The second pulse generator provides a second input signal according to the high-voltage signal. The second input signal includes the pulse signal and the sustain signal following the pulse signal. The second level shifter receives the second input signal to generate a second indication signal. The determination circuit generates a low-voltage signal according to the first indication signal and the second indication signal.