Patents Examined by Samir Ahmed
  • Patent number: 10444280
    Abstract: Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: October 15, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Dheepakkumaran Jayaraman, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Milind Sonawane, Sailendra Chadalavda, Jonathon E. Colburn, Kevin Wilder, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha
  • Patent number: 10445614
    Abstract: Systems, methods, and non-transitory computer-readable media can generate a saliency prediction model for identifying salient points of interest that appear during presentation of content items, provide at least one frame of a content item to the saliency prediction model, and obtain information describing at least a first salient point of interest that appears in the at least one frame from the saliency prediction model, wherein the first salient point of interest is predicted to be of interest to one or more users accessing the content item.
    Type: Grant
    Filed: April 16, 2017
    Date of Patent: October 15, 2019
    Assignee: Facebook, Inc.
    Inventors: Renbin Peng, Evgeny V. Kuzyakov, Chetan Parag Gupta
  • Patent number: 10440644
    Abstract: Aspects of the present disclosure provide methods, apparatus and computer program products for turbo decoder throttling (e.g., in an effort to limit power consumption by a user equipment (UE)). According to an aspect, the UE may identify an error in a received code block (CB) of a transport block (TB). The UE may enter a throttle mode in a decoder at the UE in response to the identified error, wherein the throttle mode determines how one or more subsequent CBs are processed. Numerous other aspects are provided.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: October 8, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Alexei Yurievitch Gorokhov, John Edward Smee, Michael Lee McCloud
  • Patent number: 10438684
    Abstract: A method of operating a memory system, having a non-volatile memory device, includes processing a response to a first request toward the memory device by using an original key, in response to the first request, generating and storing first parity data corresponding to the original key, and deleting the original key.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: October 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Hyeog Choi, Jun-Jin Kong, Hong-Rak Son, Pil-Sang Yoon, Chang-Kyu Seol, Ki-Jun Lee
  • Patent number: 10437666
    Abstract: In accordance with an embodiment of the invention, an IC device is disclosed. In the embodiment, the IC device includes an array of bit cells of static random-access memory (SRAM), a multi-level digitization module configured to generate a value in a range of values from a bit cell in the array of bit cells, the range of values including more than two discrete values, an output buffer configured to store the generated values, and an error correction code (ECC) decoder configured to output error corrected values based on the stored values.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: October 8, 2019
    Assignee: NXP B.V.
    Inventors: Nur Engin, Ajay Kapoor
  • Patent number: 10430927
    Abstract: In an image analyzing apparatus, a controller in a first analyzing process performs: sequentially identifying line pixel groups from a first side in a first direction; and determining whether a first-type pixel not contiguous to a first subject group constituted by at least one first-type pixel contiguous to each other in a second direction is present in a first region surrounding the first subject group, using first relevant information relating to each line pixel group located on the first side. In a second analyzing process, the controller performs: sequentially identifying the line pixel groups from a second side in the first direction; and determining whether the first-type pixel not contiguous to the first subject group is present in a second region surrounding the first subject group, using second relevant information relating to each line pixel group located on a second side.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: October 1, 2019
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Ryohei Ozawa, Kosuke Mori
  • Patent number: 10430648
    Abstract: A method for processing content in an electronic device and an electronic device for doing the same are provided. The method includes acquiring content including at least one character, and performing at least one of classifying the acquired content into at least one of a plurality of categories by analyzing the acquired content or generating vector images including a vector image corresponding to the at least one character based on the acquired content and displaying at least a part of the vector images on a display functionally connected to the electronic device.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: October 1, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Ki-Huk Lee, Seung-Cheol Lee, Jin-Hong Jeong, Tae-Gun Park, Sang-Keun Yoo, Sung-Ho Yoon
  • Patent number: 10417087
    Abstract: A system and method for adaptive multiple read of NAND flash memory. A solid state drive may employ adaptive multiple-read to perform enhanced performance error correction using soft decisions without a performance penalty that otherwise might result from performing unnecessary reads. The soft decision error correcting algorithm may employ lookup tables containing log likelihood ratios. The method may include performing one or more read operations to obtain one or more raw data words for a code word, attempting to decode the code words using the one or more raw data words, and performing additional read operations when the decoding attempt fails. This process may be repeated until a decoding attempt succeeds.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: September 17, 2019
    Assignee: NGD Systems, Inc.
    Inventor: Guangming Lu
  • Patent number: 10410738
    Abstract: According to one embodiment, a memory system includes a memory, an error correcting circuit and a memory controller. The memory includes a memory cell which is writable in a memory mode including a first mode and a second mode. The first mode is a mode in which a value of bits is written to the memory cell. The second mode is a mode in which a value of bits smaller than that in the first mode is written to the memory cell. The memory controller controls a coding rate for the error correction on the basis of result of error correction. The controller sets the first mode as the memory mode to be used. The controller changes the memory mode to be used from the first mode to the second mode in a case where the coding rate is less than a first threshold.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsuo Shono, Katsuhiko Ueki
  • Patent number: 10410370
    Abstract: An information handling system and method includes a display screen for displaying a three dimensional image captured via a three dimensional camera and the processor to detect a selection of a first pixel within the three dimensional image that is proximate to an edge of a first object in the three dimensional image and redefine the selected first pixel to snap to a second pixel within the three dimensional image on the edge of the first object, wherein the second pixel has a large disparity within the three dimensional image and the processor to detect a selection of a third pixel within the three dimensional image that is proximate to an edge of a second object in the three dimensional image and redefine the selected third pixel to snap to a fourth pixel within the three dimensional image on the edge of the second object, wherein the fourth pixel has a large disparity within the three dimensional image.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: September 10, 2019
    Assignee: Dell Products, LP
    Inventors: Jeyprakash Michaelraj, Maxwell S. Andrews
  • Patent number: 10402701
    Abstract: A face recognition system is provided that includes a device configured to capture a video sequence formed from a set of unlabeled testing video frames. The system includes a processor configured to pre-train a face recognition engine formed from reference CNNs on a still image domain that includes labeled training still image frames of faces. The processor adapts the face recognition engine to a video domain to form an adapted engine, by applying non-reference CNNs to domains including the still image and video domains and a degraded image domain. The degraded image domain includes labeled synthetically degraded versions of the frames included in the still image domain. The video domain includes random unlabeled training video frames. The processor recognizes, using the adapted engine, identities of persons corresponding to at least one face in the video sequence to obtain a set of identities. A display device displays the set of identities.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: September 3, 2019
    Assignee: NEC Corporation
    Inventors: Kihyuk Sohn, Xiang Yu, Manmohan Chandraker
  • Patent number: 10395754
    Abstract: A method is proposed for decoding read bits including information bits from memory cells of a solid state drive. The method comprises determining a reliability indication indicative of a reliability of the read bits, and iterating the following sequence of steps: soft decoding the read bits based on said reliability indication in order to obtain said information bits, determining at least one among a time indication indicative of a time elapsed since a last writing of the memory cells and a temperature indication indicative of a temperature of the memory cells, and applying at least one among said time indication and said temperature indication to said reliability indication. A corresponding solid state drive is also proposed.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: August 27, 2019
    Assignee: NandEXT Srl
    Inventor: Margherita Maffeis
  • Patent number: 10396817
    Abstract: A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: August 27, 2019
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, Abdelhakim S. Alhussein, Erich F. Haratsch
  • Patent number: 10394676
    Abstract: Provided is a generation device including: a test vector generation unit for selecting, for each of parameters to be included in a test vector, one value from among possible values for the parameter to generate test vectors whose combinations of values are different from each other; an extraction unit for extracting, as partial sequences each including one or more test vectors, portions of a series including the test vectors output by the test vector generation unit; and a test sequence generation unit for generating a test sequence based on the extracted partial sequences.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Shunichi Amano, Hisashi Miyashita, Hideki Tai
  • Patent number: 10395388
    Abstract: A system for automated geospatial image analysis comprising a deep learning model that receives orthorectified geospatial images, pre-labeled to demarcate objects of interest. The module presents marked geospatial images and a second set of unmarked, optimized, training geospatial images to a convolutional neural network. This process may be repeated so that an image analysis software module can detect multiple object types or categories. The image analysis software module receives orthorectified geospatial images from one or more geospatial image caches. Using a multi-scale sliding window submodule, image analysis software scans geospatial images, detects objects present and geospatially locates them.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: August 27, 2019
    Assignee: DigitalGlobe, Inc.
    Inventors: Adam Estrada, Andrew Jenkins, Benjamin Brock, Chris Mangold
  • Patent number: 10388393
    Abstract: The present disclosure includes apparatus and methods for debugging on a host and memory device. An example apparatus comprises a memory device having an array of memory cells. Sensing circuitry is coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry to control performance of the logical operations. An interface is configured to receive a debugging indication and to cause the controller to halt a logical operation on the memory device.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shawn Rosti
  • Patent number: 10386414
    Abstract: A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 20, 2019
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Jean-Marc Daveau, Philippe Roche, Didier Fuin
  • Patent number: 10387749
    Abstract: The present disclosure provides systems and methods that enable distance metric learning using proxies. A machine-learned distance model can be trained in a proxy space in which a loss function compares an embedding provided for an anchor data point of a training dataset to a positive proxy and one or more negative proxies, where each of the positive proxy and the one or more negative proxies serve as a proxy for two or more data points included in the training dataset. Thus, each proxy can approximate a number of data points, enabling faster convergence. According to another aspect, the proxies of the proxy space can themselves be learned parameters, such that the proxies and the model are trained jointly. Thus, the present disclosure enables faster convergence (e.g., reduced training time). The present disclosure provides example experiments which demonstrate a new state of the art on several popular training datasets.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 20, 2019
    Assignee: Google LLC
    Inventors: Yair Movshovitz-Attias, King Hong Leung, Saurabh Singh, Alexander Toshev, Sergey Ioffe
  • Patent number: 10379161
    Abstract: Various aspects of the present invention relate to scan chain stitching techniques for test-per-clock. With various implementations of the invention, a plurality of scan cell partitions are generated based on combinational paths between scan cells. Scan cells may be assigned to one or more pairs of scan cell partitions based on combinational paths between the scan cells. Each pair of the scan cell partitions comprises one stimuli partition and one compacting partition. Using the plurality of scan cell partitions generated, scan chains are formed based on at least information of combinational paths between scan cell partitions in the plurality of scan cell partitions. The formed scan chains are to be dynamically divided into three groups during a test, which are configured to operate in a shifting-launching mode, a capturing-compacting-shifting mode and a mission mode, respectively.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: August 13, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
  • Patent number: 10371510
    Abstract: The purpose of the present invention is to accurately detect, from a remote location without contact, a structure's defects such as cracking, separation, and internal cavities by distinguishing therebetween.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: August 6, 2019
    Assignee: NEC CORPORATION
    Inventor: Hiroshi Imai