Patents Examined by Sang Hui Kim
  • Patent number: 5742766
    Abstract: An operation complete signal and a convergence result signal from each processor are transferred to the X-direction interconnection switches, AND of these signals is obtained in switch units in each interconnection switch, the signal is sent out to all the Y-direction interconnection switches through a synchronizing signal relay switch and the like in each relay switch, AND of these signals is obtained in each switch unit in the interconnection switches, and the result thereof is transferred to each processor through each synchronizing signal relay switch. With this, a logical product of an operation complete signal and a logical product of a convergence result signal from all the processors are sent in parallel to all the processors.
    Type: Grant
    Filed: March 19, 1993
    Date of Patent: April 21, 1998
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering, Corp.
    Inventors: Shigeo Takeuchi, Hideo Wada, Naoki Hamanaka, Junji Nakagoshi, Teruo Tanaka, Yasuhiro Ogata, Taturu Toba, Mitsuyoshi Igai
  • Patent number: 5664222
    Abstract: An embodiment of the present invention comprises a system that causes a printer carriage to scan from a reference position to a second position. The status of the peripheral is monitored by the host computer with detectors that can sense the position of the carriage when at the reference position and the second position. A count is made of the number of clock pulses that occur during a time the carriage scans from scans reference position to the second position. A lookup table is then used that is indexed by the number of clock pulses. This provides a set of parameters the host computer will need to have available to use the peripheral right.
    Type: Grant
    Filed: November 4, 1994
    Date of Patent: September 2, 1997
    Assignee: Seiko Epson Corporation
    Inventor: Tadashi Inakoshi
  • Patent number: 5644715
    Abstract: A multimedia computer system for scheduling and coordinating distributed multimedia resources is disclosed. The scheduling and coordinating are accomplished by the operation of an algorithm in the memory of a number of networked computers. The processor, under the control of the algorithm, creates, accesses, modifies and stores a plurality of data structures in a file on a non-volatile store such as a disk. The data structures store user inputs defining the parameters associated with multimedia sessions and the scheduling information necessary to support the requirements of the sessions with a specific Quality Of Service (QOS). This information is stored on each of the computers participating in the electronic meeting for subsequent use in scheduling and implementing the sessions via an Open System Interconnect (OSI) network for example.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: July 1, 1997
    Assignee: International Business Machines Corporation
    Inventor: Mark John Baugher
  • Patent number: 5640603
    Abstract: A dynamic switch connects a control unit to a plurality of channels on one or more processors, each processor controlled by an operating system. A logical path scheduler (LPS) within a master operating system in one of the processors contains a path control table which contains an entry for each control unit, system, and logical path combination--each entry indicating current path status (connected or disconnected), and time in that status. I/O requests within the systems for which no path currently exists are queued, and the LPS initiates connections and disconnections for the paths to equitably allocate the maximum number of simultaneous path connections allowed for the control unit, among more than that maximum number of contending channels.
    Type: Grant
    Filed: January 28, 1994
    Date of Patent: June 17, 1997
    Assignee: International Business Machines Corporation
    Inventors: Allan Samuel Meritt, Andrea Lynn Sheber, Harry Morris Yudenfriend
  • Patent number: 5623643
    Abstract: A second set of telecommunication devices is arranged to substantially mirror a first set of telecommunication devices in order to provide redundancy. First and second computer modules are included, respectively, in the first and second sets of devices wherein each module is capable of providing operating system control of the system and both modules initially operating with the same operating system. Only one of the computer modules controls the system at a given time. One of the devices of each pair of devices in the first and second sets of devices is isolated from the corresponding other device. The isolated computer module is loaded with a new operating system and tested by allowing the new operating system to control the isolated devices. This permits testing of the new operating system while maintaining uninterrupted control which is provided by the other devices operating under the same operating system.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: April 22, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Paul E. Janssen, Keith W. Johnson, Gary L. Postiglione
  • Patent number: 5619682
    Abstract: A layered communications bridge mechanism connected between an upper communications layer of a first communications layer mechanism executing in a user level process and a layered communication kernel process of a second system corresponding to the next lower layers of the first communications layer mechanism. The bridge includes an upper bridge mechanism operating to appear to the lowest layer or the layers of the first communications layer mechanism to be the next lower layer of the first layered communications mechanism and a lower bridge mechanism operating to appear to the upper communications layer of the second system kernel process to be the next higher layer of the communications layers of the second system and the upper and lower bridge mechanisms operate to map between the operations of the lower layer of the first communications layer mechanism and the upper layer of the layered communications layers of the second system.
    Type: Grant
    Filed: September 28, 1993
    Date of Patent: April 8, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: Bruce D. Mayer, Martin Berkowitz, Sudershan K. Sharma
  • Patent number: 5619723
    Abstract: A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less than a full stripe optimized by selectably using the redundancy to limit the number of sectors involved, association of multiple operations with a single disk request in order to facilitate error handling, use of an access hiatus as indication of further opportunity to rebuild data in background, and scatter/scatter (bidirectional scatter/gather) operations.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: April 8, 1997
    Assignee: Dell USA Corp.
    Inventors: Craig S. Jones, Kenneth L. Jeffries, Terry J. Parks
  • Patent number: 5613159
    Abstract: In a system for data exchanges without physical contact between a generally mobile portable set and a terminal or a population of generally fixed terminals, it is sought to make a modular set comprising a portable object (notably a memory card) that can be inserted either into a transceiver device, or in an ISO reader for by example, by saving on an interface management system and by reducing the power consumption of the set to the minimum. The transceiver device is without any microprocessor, and the portable object houses means for the management notably of the transmission/reception protocol of the portable set and of the ISO 7816-3 protocol.
    Type: Grant
    Filed: March 31, 1993
    Date of Patent: March 18, 1997
    Assignee: Innovatron Industries S.A.
    Inventor: Cedric Colnot
  • Patent number: 5611048
    Abstract: A remote password administration facility operating on the network is divided in client and server programs and provides coordination between a mainframe and a network security system. A password update message is generated by the client program and transmitted across the network to a server system which acts as a gateway server to the mainframe. The password is updated at the server system in the network security system. The gateway server is coupled to a mainframe system via an emulator session. The server scans the logon profile database to determine whether the user id is authorized to access the mainframe. If so, the password update message is sent to the second security system resident in the mainframe. The server program cooperates with the emulator program to send the password update message to the mainframe security system and determine whether the password was successfully updated.
    Type: Grant
    Filed: May 9, 1994
    Date of Patent: March 11, 1997
    Assignee: International Business Machines Corporation
    Inventors: Dwayne C. Jacobs, James A. Wangler
  • Patent number: 5600824
    Abstract: A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus.
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: February 4, 1997
    Assignee: Hewlett-Packard Company
    Inventors: James B. Williams, Kenneth K. Chan, John F. Shelton, Ehsan Rashid
  • Patent number: 5596721
    Abstract: A screen communication method and system for communicating screen data between a plurality of interconnected terminal units each having a display part and an input part, wherein each time screen modifying data is input from the display part, each of the terminal units transmits a modifying right request to another terminal unit before transmitting the screen modifying data, and obtains a modifying right under such a condition that each terminal unit receives no screen modifying request from another terminal unit within a predetermined period of time after the transmission of the first modifying right request.
    Type: Grant
    Filed: September 13, 1991
    Date of Patent: January 21, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Masse, Takanori Miyamoto, Takashi Morita, Toshiro Suzuki, Eiichi Amada
  • Patent number: 5594925
    Abstract: A unit train (10) includes a base unit (12). Base unit (12) generates a clock signal and a bit signal. Base unit (12) also receives and interprets a data signal. Unit train (10) also includes a plurality of subunits (14) serially coupled in a certain order. Each subunit (14) receives the clock signal and the bit signal. Each subunit (14) also generates a portion of the data signal. Additionally each of the subunits (14) has a corresponding identity. Also included in the unit train (10) is a clock/data line (67) for relaying the clock signal and the data signal between the base unit (12) and each subunit (14).
    Type: Grant
    Filed: January 5, 1993
    Date of Patent: January 14, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Stanley D. Harder, Richard A. Houghton, Richard H. Wallace
  • Patent number: 5594896
    Abstract: Systems allowing smooth, trouble-free, "transparent" switchover from a "Primary clock" to a "Secondary clock", with no loss of clock or essential pulse-width, and where the "Secondary clock" may be completely separate from, and independent of, the "Primary clock.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: January 14, 1997
    Assignee: Unisys Corporation
    Inventor: Robert H. Carlson
  • Patent number: 5590372
    Abstract: A method for synchronous broadcasting of multiple bytes over a VME bus broadcasts multiple bytes of data across the VME bus using hardware which interfaces between the bus and attached devices. An VME address modifier code is used to identify the type of broadcast and is sent by a master device, without requiring any response from the slave devices. In a first type of broadcast an address location is transmitted over the address bus and a data message is transmitted over the data bus. In a second type of broadcast data messages are transmitted over both the data and the address buses. Multiple broadcast cycles are used to transmit the desired amount of data. An address strobe qualifies the address and data buses for a message broadcast cycle and is used by the receiving slave to clock in the message.
    Type: Grant
    Filed: July 14, 1992
    Date of Patent: December 31, 1996
    Assignee: International Business Machines Corporation
    Inventors: James N. Dieffenderfer, Bruce J. Morehead
  • Patent number: 5586256
    Abstract: A computer system includes sixteen data processors each connected to a communication bus. The communication bus comprises a data bus for carrying data, and an address bus for carrying associated labelling information uniquely identifying the data. Each processor includes read and write detectors connected to the address bus for detecting labelling information of data required by, or presently stored in, respectively, the data processor. A bulk memory having similar read and write detectors is connected to the communication bus. An address generator supplies labelling addresses to the address bus. For each address, one processor or the bulk memory supplies the corresponding data to the data bus, and other processors and/or the bulk memory requiring the data read the data from the data bus. Data is transferred between processors and/or the bulk memory in this way. The address bus and the read and write decoders are configured for multi-dimensional addressing.
    Type: Grant
    Filed: July 13, 1990
    Date of Patent: December 17, 1996
    Assignee: Akebia Limited
    Inventors: Geoffrey L. Thiel, Paul S. Pontin
  • Patent number: 5584044
    Abstract: An IC memory card for storing picture data, character data or similar data. The memory card has an input/output section connectable to a host, a storage implemented by a semiconductor memory, and a controller for writing or reading data out of the storage. The input/output section has a data terminal for receiving an address signal and a data signal each being made up of a plurality of blocks continuously, an address/data discrimination terminal for receiving a bilevel signal for discriminating the address signal and data signal fed to the data terminal from each other, a read/write discrimination terminal for receiving a bilevel signal for discriminating the read-out and write-in of data from each other, and a bus clock input terminal for receiving a bus clock synchronous to each block of the address signal or each block of the data signal.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: December 10, 1996
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Kouichi Gouhara, Kaoru Adachi, Kenji Ito, Osamu Saito
  • Patent number: 5577202
    Abstract: An automated gateway system for interfacing a first message handling system with a second message handling system. In the preferred embodiment, the automated gateway of the present invention allows the exchange between a formal system such as the United States Department of Defense AUTODIN message handling system and an informal system such as the International Standards Organization X.400 message handling system. Messages received from a first one of the message handling systems are processed and sent to a message routing unit which determines if the message should be sent to the first or second message handling system. If the second message handling system address exists, an automated gateway user agent validates the address and creates a second message handling system envelope around the entire message and submits it to the second message handling system.
    Type: Grant
    Filed: August 24, 1992
    Date of Patent: November 19, 1996
    Assignee: TRW Inc.
    Inventor: Robert D. Padgett
  • Patent number: 5577208
    Abstract: A multimedia intercommunications installation suitable for conveying animated images between a plurality of users each provided with a microcomputer type of workstation. Each user is provided with a new central unit which processes the pixels for the screen directly. The new CPU receives and forwards data concerning animated images, sound, and writing. The writing data is advantageously generated by the writing members already provided for the workstation.
    Type: Grant
    Filed: June 23, 1992
    Date of Patent: November 19, 1996
    Assignee: Alcatel NV
    Inventor: Patrice Couturier
  • Patent number: 5574949
    Abstract: In a multi-access local area network, a plurality of stations employing a predetermined protocol (e.g., a protocol based on a CSMA/CD system) are linked together by a bus. In order to transmit MIDI data in the multi-access local area network, another station employing a certain protocol which is suitable for transmitting the MIDI data is further provided and is designed to perform a frequency modulation by a unit of word. The protocol employed by another station defines a specific frame form which is based on a start-stop system. The specific frame form contains a sequence of a preamble, a start bit, a data portion and a stop bit. An optimum bit pattern which is suitable for the transmission of the MIDI data is selected for the preamble.
    Type: Grant
    Filed: December 6, 1993
    Date of Patent: November 12, 1996
    Assignee: Yamaha Corporation
    Inventor: Kanehisa Tsurumi
  • Patent number: 5564042
    Abstract: A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entry signals intent to use the bus.A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entity signals intent to use the bus.
    Type: Grant
    Filed: February 3, 1994
    Date of Patent: October 8, 1996
    Assignee: International Business Machines Corporation
    Inventors: Sebastian T. Ventrone, Timothy J. VonReyn