Abstract: An Input/Output Module (IOM) interfacing multiple computers attached to a dual system bus. The IOM provides an interbus module which interfaces the dual system bus to a sub-requestor bus connecting multiple sub-requestor modules. The sub-requestor modules control a plurality of interface adaptors permitting data transfers to/from a variety of peripherals using different data protocols and clock rates. The requirements for the main host processors and memories in a computer system would be unduly burdensome were it not for the relief from these overhead operations by the input/output module which provides the tailoring of data transfer capability to and from a multiplicity of peripherals having many different types of protocols and clock rates.

Abstract: A Time Reference Manager for providing a time reference value to the nodes of a ring topology local area network. A time reference is implemented on a distributed system data bus at a low level interface to provide highly accurate time reference values at each node of the LAN with no settling time required. One node on the network is designated as the Time Reference Manager and broadcasts the Time Reference Protocol data around the ring of the LAN network. Time delay correction is provided by an algorithm performed in a time reference software process. Clock accuracy is selectable by the number of bits used in the clock-counter.

Abstract: Systems allowing smooth, trouble-free, "transparent" switchover from a "Primary clock" to a "Secondary clock", with no loss of clock or essential pulse-width, and where the "Secondary clock" may be completely separate from, and independent of, the "Primary clock.

Abstract: An I/O controller for transferring data between a host processor and one or more I/O units. The controller interleaves processor command transfers (PIO) in the midst of direct memory access (DMA) transfers without repeated data moves. DMA transfers are suspended temporarily during the priority PIO transfer. An interrupt Scanner, for scanning the various I/O units, is also prioritized with respect to DMA and PIO transfers.

Abstract: In the system of the present invention, a specialized form of read-ahead, write-behind buffering is provided which enables the host processing system to provide timely responses to device requests that are emulated by the host processor. Each input/output device request is identified by an address to which the device is purportedly mapped to. This address is translated to an address containing a status word for that particular device being emulated. Each status word contains a byte of information either to be sent to the microprocessor as a response during an I/O read operation request by the microprocessor, or to receive data written by the microprocessor in response to an I/O write operation request, and a plurality of status bits which identify the state of the data contained in the I/O status word.

Abstract: In a clock generating apparatus or clock generator employing PLL (phase-locked loop) by controlling a VCO (voltage controlled oscillator) in response to an output obtained by phase-comparing a clock signal based on an output signal of the VCO with an externally applied timing signal, a range of an oscillating frequency of VCO is varied in accordance with a frequency variation in the timing signal. A clock generating apparatus is provided for each of plural information processing sections, so as to surely synchronize operations of data processings including data transfers between the respective sections. When a clock signal is distributed to each of the information processing sections, the clock signal outputted from the distributing circuit is phase-compared in order to control the VCO.

Abstract: A generic process for combining the support of multiple formats and protocols (FAPs) for simultaneous communication between a controller and an attached device over the same port is described. The transmission medium between the two units is a two-wire type cable, i.e., twisted pair, coaxial, etc., generically referred to as "Coax". The controller and the attached device each support their own collection of Coax FAPs, which may or may not be different. In accordance with the process, information is exchanged between the controller and the device identifying the particular Coax FAPs each respective unit supports and a set of Coax FAPs common to the controller and the device is identified. A communication buffer common to the controller and the device is configured for supporting the set of common Coax FAPs. Each Coax FAP may be independently enabled or disabled.

Abstract: An IC recording medium for executing data transmission/reception without contact with a reader/writer.

Abstract: A prefetch buffer adapted to be installed between a cache memory and a main memory in a computer system having a CPU. The prefetch buffer includes a buffer storage having at least one entry for storing prefetched data and an address tag, which is to be used for searching the data, as a pair; a data searcher for searching, from the data stored in the buffer storage, for data having an address requested by the CPU; and an address estimator for determining an address of data to be prefetched next from the main memory, based on the address requested by the CPU and also on a history of the addresses of data prefetched in the past from the main memory; and an address generator for generating an address of data to be prefetched from the main memory. With this arrangement, it is possible to improve the hit ratio of the prefetch buffer regardless of the direction in which the access address varies.

Abstract: A controllable configuration management (CFM) state machine user interface is disclosed for use in the physical layer controller of a station or concentrator capable or insertion into a data transmission network that is capable of operating substantially in accordance with the FDDI protocol. In one aspect of the invention, the physical layer controller includes a null configuration register, a join configuration register and a loop configuration register. The null configuration register is capable of storing information indicative of a desired configuration of the physical layer controller when the CFM state machine is in a null configuration. Similarly, the join and loop configuration register are capable of storing information indicative of desired configurations when the CFM state machine is in the join and loop configurations respectively.

Abstract: An apparatus which receives locking signals from a first device and provides a lengthened version of certain of these signals to a second device. The apparatus stretches the locking signal provided to ensure that the signal remains valid throughout the entire locked sequence. The apparatus also indicates when arbitration windows are available between back-to-back locked cycles, i.e. when it is okay to relinquish control of the host bus to a requesting bus master or device. The apparatus monitors cache controller activity and notifies arbitration logic when the last write cycle of a read-modify-write sequence or multiple transfer write cycle begins. When the cycle completes, the arbitration logic releases the bus, thus providing an arbitration window for other requesting bus masters and devices. In this manner, overlock conditions which block bus masters from obtaining control of the bus are prevented from occurring.

Abstract: A bidirectional interrupt technique and mechanism is described for handling programmable length interrupt messages between two devices, preferably both processors, through dual, programmably defined memory queues. The technique and mechanism automatically updates a read and write address counter, a queue count register, and an interrupt count register for each direction of the flow of interrupts.

Abstract: Method and apparatus in a communications controller to transfer data between a host computer and the controller. The communications controller includes a channel adapter (CA) and a central control unit (CCU) for controlling the operation of the CA. In response to a request from the CCU, the channel adapter transfers data between the host computer and the channel adapter to or from a linked list of buffers until all messages contained in the linked list have been transferred. Only after all messages in the present transmission have been transferred, the CA interrupts the CCU to signal completion. In a preferred embodiment, the channel adapter includes a microprocessor and a read-only-memory containing programmed instructions for controlling the microprocessor. Together, the microprocessor under control of the read-only-memory instructions form an apparatus for carrying out the method.

Abstract: A method for synchronizing a distributed multiple clock system in which the first clock to reach a first predetermined number of counts generates a polling request signal. The remaining clocks compare the content of their counters to determine if they are in synchronization with the clock that generated the polling request signal. Each clock will place itself inactive if it determines it is out of synchronization with the active clocks. The first active clock to reach a second predetermined number of counts will generate a synchronization interrupt signal which resets a counter in each clock to zero. A start subroutine readmits inactive clocks when after a synchronization interrupt signal is generated its counts are within a predetermined readmittance range or its counter counts up to a third predetermined value.