Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device can assign each of a plurality of superblocks to one of a plurality of groups. The processing device can monitor an order that each of the groups have been written to. The processing device can write data to a first block of a first superblock of a first of the plurality of groups.

Abstract: Devices, systems, and methods are provided that cause a controller to receive a first command to read or write first data from or to a first logical address; and determine a first mapped logical address that the first logical address is mapped to. A first plurality of logical addresses is mapped to the first mapped logical address and includes the first logical address. The controller reads a first data structure at the first mapped logical address. The first data structure includes a pointer to a first intermediate physical address. The controller reads a second data structure at the first intermediate physical address. The second data structure includes a plurality of pointers to target physical addresses. The plurality of pointers includes a pointer to a first target physical address for the first logical address. The controller reads or writes the first data from or to the first target physical address.

Abstract: Provided are a computer program product, system, and method for saving track metadata format information for tracks demoted from cache for use when the demoted track is later staged into cache. A track is demoted from the cache and indicated in a demoted track list. The track format information for the demoted track is saved, wherein the track format information indicates a layout of data in the track. The saved track format information for the demoted track is used when the demoted track is staged back into the cache.

Abstract: Virtual memory space may be saved in a clone environment by leveraging the similarity of the data signatures in swap files when a chain of virtual machines (VMs) includes clones spawned from a common parent and executing common applications. Deduplication is performed across the chain, rather than merely within each VM. Examples include generating a common deduplication identifier (ID) for the chain; generating a logical addressing table linked to the deduplication ID, for each of the VMs in the chain; and generating a hash table for the chain. Examples further include, based at least on a swap out request, generating a hash value for a block of memory to be written to a storage medium; and based at least on finding the hash value within the hash table, updating the logical addressing table to indicate a location of a prior-existing duplicate of the block on the storage medium.

Abstract: The memory system is provided to include a memory device, and a memory controller configured to control the memory device. The memory controller is configured to transmit, after the host completes a first initial setting operation for the memory system, mapping information between a logical address and a physical address to a host in order to load the mapping information between the logical address and the physical address into a host memory area located in the host, and to transmit, before the host executes a second initial setting operation for the memory system, to the host, updated mapping information between the logical address and the physical address to update, based on a change made to the host memory area.

Abstract: A processing device, operatively coupled with the memory device, is configured to provide a plurality of functions for accessing the memory device, wherein a function of the plurality of function receives input/output (I/O) operations from a host computing system. The processing device further determines a quality of service level of each function of the plurality of functions, and assigns to each function of the plurality of functions a corresponding function weight based on a corresponding quality of service level. The processing device also selects, for execution, a subset of the I/O operations, the subset comprising a number of I/O operations received at each function of the plurality of functions, wherein the number of I/O operations is determined according to the corresponding function weight of each function. The processing logic then executes the subset of I/O operations at the memory device.

Abstract: A memory management unit comprises an interface for receiving an address translation request from a device, the address translation request specifying a virtual request to be translated. Translation circuitry translates the virtual address into an intermediate address different from a physical address directly specifying a memory location. The interface provides an address translation response specifying the intermediate address to the device in response to the address translation request. This improves security by avoiding exposure of physical addresses to the device.

Abstract: An integrated circuit device includes a nonvolatile memory, first and second buffer memories, and a controller. Each of the first and second buffer memories is configured to buffer write data to be written to the nonvolatile memory in response to a write request and also buffer read data received from the nonvolatile memory in response to a read request. A controller is provided, which evaluates the first buffer memory against at least one criterion relating to data accuracy. The controller is configured to: redirect at least some of the write data from the first buffer memory to the second buffer memory in response to the write request when the evaluation demonstrates the criterion has been exceeded, and redirect at least some of the read data from the first buffer memory to the second buffer memory in response to the read request when the evaluation demonstrates the criterion has been exceeded.

Abstract: A neural processing device and transaction tracking method thereof are provided. The neural processing device comprises a first set of a plurality of neural cores, a shared memory shared by the first set of the plurality of neural cores, and a programmable hardware transactional memory (PHTM) configured to receive a memory access request directed to the shared memory from the first set of the plurality of neural cores and configured to commit or buffer the memory access request.

Abstract: A processing device in a memory sub-system initiates read operations on each of a plurality of segments in a first region of the memory device during a first time interval, wherein at least a subset of the plurality of segments in the first region of the memory device are storing host data. The processing device further receives, as a result of at least one read operation, at least one data signal from a corresponding one of the plurality of segments in the first region of the memory device, and performs a signal calibration operation using the at least one data signal to synchronize one or more relevant signals with a reference clock signal used by the processing device.

Abstract: A memory apparatus and a data rearrangement method for computing in memory (CIM) are provided. The method includes determining whether first sequence data has two target bits that are both of a first value, inserting a non-target bit of a second value between the two target bits that are both of the first value and adjacent to each other to generate second sequence data, and receiving the second sequence data through memory cells in a memory to perform a multiply-accumulate (MAC) operation on the second sequence data. Each bit in the first sequence data is the first value or the second value. One of the two target bits is located adjacent to the other one of the two target bits in the first sequence data. The two target bits and the non-target bit are located in the first sequence data. Accordingly, the error rate is decreased.

Abstract: Apparatuses, systems, and methods for managing storage and retrieval of metadata at a memory. A metadata column address generator, during an metadata access operation, is configured to decode a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of column planes of a memory array. A column decoder is configured to facilitate a double cycle access operation to write data to or retrieve data from the plurality of column planes based on the column address and to write metadata to or retrieve metadata from a particular column corresponding to the metadata column address of the particular one of the column planes corresponding to the column plane address.

Abstract: Techniques for rebuilding space accounting counters in mapping layers of storage appliances. The techniques include uniquely associating top levels of a mapping layer of a storage appliance with respective storage objects. The techniques further include determining amounts of logical storage space consumed by the respective storage objects from mappings of LBAs of the respective storage objects to virtual blocks of a virtual layer of the storage appliance. The techniques further include determining amounts of physical storage space consumed by the respective storage objects from logged information pertaining to each leaf pointer of a leaf level of the mapping layer that points to a virtual block in the virtual layer, each virtual block being mapped to a physical block in a physical layer of the storage appliance. The techniques further include using multi-threading to determine amounts of logical storage space consumed by dynamically adjustable ranges of the respective storage objects.

Abstract: A storage device including a memory controller and an operating method of the memory controller are provided. The storage device includes a non-volatile memory device including a write buffer configured to store write data provided from a host and a journal buffer configured to store a journal log, a volatile memory device configured to temporarily store metadata, and a memory controller configured to provide the non-volatile memory device with a journaling command, that includes the journal log and the physical address corresponding to the journal buffer, and which issues a command to store the journal log in the journal buffer, to update the metadata temporarily stored in the volatile memory device, and to control the volatile memory device to store updated metadata to the non-volatile memory device.

Abstract: It is possible to reduce analysis cost of a management system. The management system includes a CPU and manages one or more storage devices that provide, to a higher-level device, one or more volumes for inputting and outputting data. The CPU is configured to collect performance information of the volume from the storage device at a predetermined first time interval and detect a QoS violation of the performance information of the volume at a second time interval longer than the first time interval.

Abstract: A method for distributed file deletion or truncation, performed by a storage system, is provided. The method includes determining, by an authority owning an inode of a file, which authorities own data portions to be deleted, responsive to a request for the file deletion or truncation. The method includes recording, by the authority owning the inode, the file deletion or truncation in a first memory, and deleting, in background by the authorities that own the data portions to be deleted, the data portions in one of a first memory or a second memory. A system and computer readable media are also provided.

Abstract: An interface of a memory sub-system can receive a write command addressed to a first address and a read command addressed to a second address and can receive data corresponding to the write command. The interface can determine whether the first address matches the second address responsive to determining that the first address matches the second address, can drop the read command and the second address, and can provide the data to a host.

Abstract: A method includes determining respective memory access counts of a plurality of blocks of non-volatile memory cells that are grouped into a plurality of respective groups, comparing the respective memory access counts to respective memory access thresholds, determining a respective memory access count of a block of non-volatile memory cells exceeds a respective memory access threshold, and performing a media scan operation on the block of non-volatile memory cells.

Abstract: Disclosed approaches for emulating flash memory include storage circuits having respective address decoders. An input-output circuit has pins compatible with a flash memory device and is configured to input flash commands and output response signals via pins. An emulator circuit is configured to translate each flash command into one or more storage-circuit commands compatible with one storage circuit of the storage circuits, and to generate response signals compatible with the flash memory device. A translator circuit is configured to map a flash memory address in each flash command to an address of the one storage circuit, and to transmit the one or more storage-circuit commands and address to the one storage circuit.

Abstract: A memory system includes a memory device including a plurality of memory dies that store data, and a controller coupled to the plurality of memory dies through a plurality of channels, and suitable for generating and managing map data in which a logical address of a host is corresponding to a physical address of the memory device, wherein, when logical information on two or more consecutive logical addresses requested to be accessed and physical information on two or more consecutive physical addresses corresponding to the two or more consecutive logical addresses are inputted from the host, the controller sequentially performs access operations on the physical addresses corresponding to the received physical information.