Abstract: Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments for supporting processor capabilities may be configured to support a multi-mode indexed cache for a processor. Various example embodiments for supporting a multi-mode indexed cache for a processor may be configured to support a multi-mode indexed cache configured as a set associative cache having a plurality of sets, where the cache is configured to support multiple indexing modes for indexing memory blocks such that, for a memory operation for a memory block, the multiple indexing modes are configured to cause selection of different ones of the plurality of sets of the cache for the memory operation for the given memory block.

Abstract: An adaptive collaboration platform is described. In accordance with the described techniques, a request is received to generate collaboration recommendations for an artist. A collaboration system processes artist data for the artist with additional artist data for other artists in an artist population to generate collaboration recommendations for the artist. The collaboration recommendations are exposed to the artist via a user interface of the collaboration system. The collaboration recommendations recommend at least one of the other artists as a collaborator for the artist. The user interface of the collaboration system also enables the artist to form a communication channel with the collaborator.

Abstract: Techniques are disclosed to migrate data via query co-evaluation. In various embodiments, an input data associated with a source database S and a target schema T to which the input data is to be migrated is received. A set of relational conjunctive queries from target schema T to source database S is received. Query co-evaluation is performed on the received set of relational conjunctive queries to transition data from source database S to target schema T.

Abstract: An analytics engine is described that can receive data associated with use of a content item in a content management system and measure a use of content management system resources required to maintain the content item. Values of a usage metric can be assigned to the content item based on the received data associated with the use of the content item. A database schema can be generated by the analytics engine that is configured to reduce the use of content management system resources required to maintain the content item. The database schema can be provided to the content management system for implementation in a database associated with the content management system.

Abstract: Memory modules and associated devices and methods are provided using a memory copy function between a cache memory and a main memory that may be implemented in hardware. Address translation may additionally be provided.

Abstract: Arrangements for controlling data retrieval are provided. In some aspects, a data request may be received by a computing platform. A pre-fetch engine may be executed to analyze the data request and generate, using a machine learning model, a pre-fetch template identifying data sets responsive to the request. The pre-fetch template may be transmitted to one or more data repositories and at least one data repository may transmit response data sets to the computing platform. An issue in the mesh network through which the data sets are transmitted may be detected and the data sets may be stored at a data silo associated with a node of the mesh network. An alternate transmission path may be generated and the data may be transmitted from the data silo of the node to another node in the mesh network based on the alternate transmission path.

Abstract: Aspects of the present disclosure provide techniques for predicting content relevant to questions based on reference links. Embodiments include receiving a set of question and answer (Q/A) pairs and identifying a set of references in the set of Q/A pairs that link pairs of Q/A pairs of the set of Q/A pairs. Embodiments include identifying popular Q/A pairs of the set of Q/A pairs based on the set of references. The popular Q/A pairs may be referenced by a subset of the set of Q/A pairs and each respective Q/A pair of the subset of the set of Q/A pairs may comprise a respective question of a plurality of questions. Embodiments include training a model based on the plurality of questions, the popular Q/A pairs, and the set of references, to predict Q/A pairs of the set of Q/A pairs that are relevant to a given question.

Abstract: A method to obtain a cache miss ratio curve where a memory blocks of a cache have variable block sizes. By stacking sets of counters, each set being for a different block size, a stack distance for variable block sizes can be obtained and used to determine a miss ratio curve. Such curve can then be used to select a cache size that is appropriate for an application without requiring excessive memory. Methods can be used for batches of request, can apply limits to block sizes, and rounding for intermediary block sizes, they can be used with pruning, and their space complexity can be held constant.

Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device can assign each of a plurality of superblocks to one of a plurality of groups. The processing device can monitor an order that each of the groups have been written to. The processing device can write data to a first block of a first superblock of a first of the plurality of groups.

Abstract: Devices, systems, and methods are provided that cause a controller to receive a first command to read or write first data from or to a first logical address; and determine a first mapped logical address that the first logical address is mapped to. A first plurality of logical addresses is mapped to the first mapped logical address and includes the first logical address. The controller reads a first data structure at the first mapped logical address. The first data structure includes a pointer to a first intermediate physical address. The controller reads a second data structure at the first intermediate physical address. The second data structure includes a plurality of pointers to target physical addresses. The plurality of pointers includes a pointer to a first target physical address for the first logical address. The controller reads or writes the first data from or to the first target physical address.

Abstract: Provided are a computer program product, system, and method for saving track metadata format information for tracks demoted from cache for use when the demoted track is later staged into cache. A track is demoted from the cache and indicated in a demoted track list. The track format information for the demoted track is saved, wherein the track format information indicates a layout of data in the track. The saved track format information for the demoted track is used when the demoted track is staged back into the cache.

Abstract: Virtual memory space may be saved in a clone environment by leveraging the similarity of the data signatures in swap files when a chain of virtual machines (VMs) includes clones spawned from a common parent and executing common applications. Deduplication is performed across the chain, rather than merely within each VM. Examples include generating a common deduplication identifier (ID) for the chain; generating a logical addressing table linked to the deduplication ID, for each of the VMs in the chain; and generating a hash table for the chain. Examples further include, based at least on a swap out request, generating a hash value for a block of memory to be written to a storage medium; and based at least on finding the hash value within the hash table, updating the logical addressing table to indicate a location of a prior-existing duplicate of the block on the storage medium.

Abstract: A processing device, operatively coupled with the memory device, is configured to provide a plurality of functions for accessing the memory device, wherein a function of the plurality of function receives input/output (I/O) operations from a host computing system. The processing device further determines a quality of service level of each function of the plurality of functions, and assigns to each function of the plurality of functions a corresponding function weight based on a corresponding quality of service level. The processing device also selects, for execution, a subset of the I/O operations, the subset comprising a number of I/O operations received at each function of the plurality of functions, wherein the number of I/O operations is determined according to the corresponding function weight of each function. The processing logic then executes the subset of I/O operations at the memory device.

Abstract: The memory system is provided to include a memory device, and a memory controller configured to control the memory device. The memory controller is configured to transmit, after the host completes a first initial setting operation for the memory system, mapping information between a logical address and a physical address to a host in order to load the mapping information between the logical address and the physical address into a host memory area located in the host, and to transmit, before the host executes a second initial setting operation for the memory system, to the host, updated mapping information between the logical address and the physical address to update, based on a change made to the host memory area.

Abstract: A memory management unit comprises an interface for receiving an address translation request from a device, the address translation request specifying a virtual request to be translated. Translation circuitry translates the virtual address into an intermediate address different from a physical address directly specifying a memory location. The interface provides an address translation response specifying the intermediate address to the device in response to the address translation request. This improves security by avoiding exposure of physical addresses to the device.

Abstract: An integrated circuit device includes a nonvolatile memory, first and second buffer memories, and a controller. Each of the first and second buffer memories is configured to buffer write data to be written to the nonvolatile memory in response to a write request and also buffer read data received from the nonvolatile memory in response to a read request. A controller is provided, which evaluates the first buffer memory against at least one criterion relating to data accuracy. The controller is configured to: redirect at least some of the write data from the first buffer memory to the second buffer memory in response to the write request when the evaluation demonstrates the criterion has been exceeded, and redirect at least some of the read data from the first buffer memory to the second buffer memory in response to the read request when the evaluation demonstrates the criterion has been exceeded.

Abstract: A neural processing device and transaction tracking method thereof are provided. The neural processing device comprises a first set of a plurality of neural cores, a shared memory shared by the first set of the plurality of neural cores, and a programmable hardware transactional memory (PHTM) configured to receive a memory access request directed to the shared memory from the first set of the plurality of neural cores and configured to commit or buffer the memory access request.

Abstract: A processing device in a memory sub-system initiates read operations on each of a plurality of segments in a first region of the memory device during a first time interval, wherein at least a subset of the plurality of segments in the first region of the memory device are storing host data. The processing device further receives, as a result of at least one read operation, at least one data signal from a corresponding one of the plurality of segments in the first region of the memory device, and performs a signal calibration operation using the at least one data signal to synchronize one or more relevant signals with a reference clock signal used by the processing device.

Abstract: A memory apparatus and a data rearrangement method for computing in memory (CIM) are provided. The method includes determining whether first sequence data has two target bits that are both of a first value, inserting a non-target bit of a second value between the two target bits that are both of the first value and adjacent to each other to generate second sequence data, and receiving the second sequence data through memory cells in a memory to perform a multiply-accumulate (MAC) operation on the second sequence data. Each bit in the first sequence data is the first value or the second value. One of the two target bits is located adjacent to the other one of the two target bits in the first sequence data. The two target bits and the non-target bit are located in the first sequence data. Accordingly, the error rate is decreased.

Abstract: Apparatuses, systems, and methods for managing storage and retrieval of metadata at a memory. A metadata column address generator, during an metadata access operation, is configured to decode a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of column planes of a memory array. A column decoder is configured to facilitate a double cycle access operation to write data to or retrieve data from the plurality of column planes based on the column address and to write metadata to or retrieve metadata from a particular column corresponding to the metadata column address of the particular one of the column planes corresponding to the column plane address.