Patents Examined by Sanjiv Shah
  • Patent number: 10262721
    Abstract: The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel controller coupled to the memory device. The channel controller is configured to cause a bulk invalidate command to be sent to a cache memory system responsive to receipt of a bit vector operation request.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: April 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Richard C. Murphy
  • Patent number: 9946718
    Abstract: An apparatus may include a processor component caused to: generate map entries in map data descriptive of encrypted data blocks within a data file; use first map block encryption data to encrypt a first map extension of the map data; transmit the encrypted first map extension for storage within the data file; store the first map block encryption data within the second map extension; use second map block encryption data to encrypt a second map extension of the map data after storage of the first map block encryption data therein; transmit encrypted second map extension for storage within the data file; store the second map block encryption data within the map base; use third map block encryption data to encrypt a map base of the map data after storage of the second map block encryption data therein; and transmit the encrypted map base for storage within the data file.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: April 17, 2018
    Assignee: SAS Institute Inc.
    Inventors: Brian Payton Bowman, Mark Kuebler Gass, III
  • Patent number: 9946719
    Abstract: An apparatus includes a processor component of a first node device caused to receive data block encryption data and an indication of size of an encrypted data block distributed to the first node device for decryption, and in response to the data set being of encrypted data: receive an indication of the quantity of sub-blocks within the encrypted data block, and a hashed identifier for each data sub-block; use the data block encryption data to decrypt the encrypted data block to regenerate data set portions from the data sub-blocks; analyze the hashed identifier of each data sub-block to determine whether all data set portions are distributed to the first node device for processing; and in response to a determination that at least one data set portion is to be distributed to a second node device for processing, transmit the at least one data set portion to the second node device.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: April 17, 2018
    Assignee: SAS Institute Inc.
    Inventors: Brian Payton Bowman, Mark Kuebler Gass, III
  • Patent number: 9898361
    Abstract: Methods and apparatus are provided for multi-tier detection and decoding in flash memory devices. Data from a flash memory device is processed by obtaining one or more read values for at least one bit in a given page of the flash memory device; converting the one or more read values for the at least one bit to a reliability value; performing an initial decoding of the at least one bit in a given page using the reliability value; and performing an additional decoding of the at least one bit in the given page if the initial decoding is not successful, wherein the additional decoding uses one or more of additional information for the given page and at least one value for at least one bit from at least one additional page.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: February 20, 2018
    Assignee: Seagate Technology LLC
    Inventors: Erich F. Haratsch, Abdel Hakim S. Alhussien
  • Patent number: 9880543
    Abstract: A method for transmitting and receiving data between a micro processing unit (MPU) and a memory operating with different operating voltages in a programmable logic controller (PLC) is provided. In one embodiment, the method includes outputting, by the MPU, a chip select (CS) signal and an address signal to read requested data from the memory, outputting, by an OR gate, an activation signal for activating a data input buffer, the OR gate receiving the CS signal and the address signal, and outputting, by an access signal output buffer, a memory access signal for operation of the memory, the access signal output buffer receiving the CS signal and the address signal. The method further includes outputting the requested data to the data input buffer, and outputting, by the data input buffer, the requested data to the MPU when the requested data is received by the data input buffer from the memory.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 30, 2018
    Assignee: LSIS CO., LTD.
    Inventor: Jo Dong Park
  • Patent number: 9870400
    Abstract: Analyzing a managed runtime cache is provided. A heap associated with a managed runtime environment, where the heap includes an N-generation cache or a plurality of objects associated with a program operating within a managed runtime environment is identified. A snapshot of the heap is produced, wherein the snapshot identifies a memory location for each object of the plurality of objects at which the object is stored. A generation of each of the plurality of objects based, at least in part, on the memory location of the object is determined. One or more suggestions based, at least in part, on the memory location of the plurality of objects is provided.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Richard N. Chamberlain, Howard J. Hellyer, Matthew F. Peters, Adam J. Pilkington
  • Patent number: 9830094
    Abstract: A system, method, and computer program product is described for providing dynamic enabling and/or disabling of protection information (PI) in array systems during operation. A storage system receives a request to transition a volume from PI disabled to PI enabled during regular operation. The storage system synchronizes and purges the cache associated with the target volume. The storage system initiates an immediate availability format (IAF-PI) process to initialize PI for the associated data blocks of the volume's storage devices. The storage system continues receiving I/O requests as the IAF-PI process sweeps through the storage devices. The storage system inserts and checks PI for the write data as it is written to the storage devices. The storage system inserts PI for requested data above the IAF-PI boundary and checks PI for requested data below the IAF-PI boundary. The transition remains an online process that avoids downtime.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: November 28, 2017
    Assignee: NetApp, Inc.
    Inventors: Mahmoud K. Jibbe, Charles D. Binford, Wei Sun
  • Patent number: 9753813
    Abstract: Persistent storage for a master copy is provided using operation numbers. A master copy can include a persistent key-value store such as a B-tree with references to corresponding data. When provisioning a slave copy, the master copy sends a point-in-time copy of the B-tree to the slave copy, which stores a copy of the B-tree, allocates the necessary space, and updates the references of the B-tree to point to a local storage before the data is transferred. When writing the data to persistent storage, a snapshot created on the master copy is an operation that is replicated to the slave copy. The snapshot is generated using a volume view that includes changes to chunks of data of the master copy since a previous snapshot, as determined using the operation number for the previous snapshot. Data (and metadata) for the snapshot is written to persistent storage while new EO operations are processed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 5, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Jianhua Fan, Benjamin Arthur Hawks, Norbert Paul Kusters, Nachiappan Arumugam, Danny Wei, John Luther Guthrie, II
  • Patent number: 9746986
    Abstract: A storage system includes a plurality of storage devices, including a first storage device and an information processor apparatus for managing the storage system. The first storage device is configured to select a second storage device coupled over a network with the information processor apparatus from among the plurality of storage devices, and assign a representative address such as an Internet Protocol (IP) address to be used for communication with the information processor apparatus to the selected second storage device. The second storage device is configured to receive a request addressed to the representative address from the information processor apparatus, and transfer the request to a third storage device among the plurality of storage devices to process the request. An assigned representative address may be canceled when a storage device fails and an internal IP address may be assigned. Storage devices may be selected based on load and the need for cable or hardwired connections may be reduced.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 29, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Kuwayama, Tsuyoshi Uchida
  • Patent number: 9632929
    Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: April 25, 2017
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Patent number: 9563359
    Abstract: A system is provided for transforming an in-use RAID array from a first array configuration having a first parameter to a second array configuration having a second parameter while preserving a logical data structure of the RAID array. The system includes an extent reservation component, and a data migration component for reading unmigrated data from an area of an array arranged according to the first array configuration and writing the data to an area of the array arranged according to the second array configuration using reserved extents to store migrated data. The system also includes a first I/O component for performing I/O according to the first array configuration on unmigrated data prior to its reading by the data migration component, and a second I/O component for performing I/O according to the second array configuration on the migrated data after writing the migrated data.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joanna K. Brown, Matthew J. Fairhurst, William J. Scales, Mark B. Thomas
  • Patent number: 9558085
    Abstract: An administrator provisions a virtual disk in a remote storage platform and defines policies for that virtual disk. A virtual machine writes to and reads from the storage platform using any storage protocol. Virtual disk data within a failed storage pool is migrated to different storage pools while still respecting the policies of each virtual disk. Snapshot and revert commands are given for a virtual disk at a particular point in time and overhead is minimal. A virtual disk is cloned utilizing snapshot information and no data need be copied. Any number of Zookeeper clusters are executing in a coordinated fashion within the storage platform, thus increasing overall throughput. A timestamp is generated that guarantees a monotonically increasing counter, even upon a crash of a virtual machine. Any virtual disk has a “hybrid cloud aware” policy in which one replica of the virtual disk is stored in a public cloud.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: January 31, 2017
    Assignee: Hedvig, Inc.
    Inventor: Avinash Lakshman
  • Patent number: 9552170
    Abstract: The memory area managing unit 22 (a) sets a protect flag to each virtual area allocated in a virtual memory space, the protect flag indicating whether a use of the virtual area has been finished or not, and (b) when a part or all of a first virtual area would overlap another second virtual area due to expansion or movement of the first virtual area, allows the expansion or the movement of the first virtual area accompanying with overlapping the second virtual area, if the protect flag of the second virtual area indicates that a use of the second virtual area has been finished. If the expansion or the movement is allowed, the memory pool managing unit 23 adds a physical area in a physical memory space corresponding to an overlapping part of the first and second virtual areas into a memory pool to map to another virtual area.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: January 24, 2017
    Assignee: Kyocera Document Solutions, Inc.
    Inventors: Masato Tanba, Takashi Toyoda
  • Patent number: 9535834
    Abstract: An electronic device includes a semiconductor device, wherein the semiconductor device includes: a word line driving unit for driving a plurality of word lines; a first cell array arranged at one side of the word line driving unit; a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit, arranged between the first cell array and the second cell array, for generating a bias voltage based on currents flowing through the first reference resistance element included in the first cell array and the second reference resistance element included in the second cell array; a first read control unit; and a second read control unit.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: January 3, 2017
    Assignees: SK Hynix Inc., Kabushiki Kaisha Toshiba
    Inventors: Dong-Keun Kim, Masahiro Takahashi, Tsuneo Inaba
  • Patent number: 9529983
    Abstract: A solid state memory unit and method for protecting a solid state memory having a microprocessor are disclosed. The method may include receiving user-input requests for access to blocks of the solid state memory, the blocks of the solid state memory storing ordered virtual files. The user-input requests may have a respective sequence of virtual file position values. The method may include comparing the sequence of virtual file position values with a predetermined sequence of virtual file position values to verify the user-input requests, and when the sequence of virtual file position values equals the predetermined sequence of virtual file position values, responding to, via the microprocessor, requests for access to the blocks of the solid state memory to decrypt and transfer requested files stored. The predetermined sequence may correspond to a predetermined sequence of requests for access to files that can be selected by the user.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: December 27, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Francesco Varone
  • Patent number: 9489145
    Abstract: A disk drive includes a controller and at least one disk, which may include a first I-region, a second I-region, and an E-region. The first and second I-region may have a first final logical block address (LBA) and a second final LBA, respectively. The controller may be configured to cause information to be written to the first I-region and the second I-region using a first type and a second type of magnetic recording, respectively. The controller also may be configured to set at least one of the first final LBA or the second final LBA to a final LBA value higher than the at least one of the first final LBA or the second final LBA, respectively, after writing user data to at least a portion of the first I-region or the second I-region and without removing the user data.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: November 8, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Jonathan Darrel Coker, David Robison Hall
  • Patent number: 9436599
    Abstract: A data storage device with a FLASH memory accessed via multiple channels and a FLASH memory control method are disclosed. The control method includes dividing a plurality of blocks of a FLASH memory into groups to be accessed by a plurality of channels separately, each block comprising a plurality of pages; allocating a random access memory to provide a first set of cache spaces for the different ones of the plurality of channels; separating write data issued from a host to correspond to the plurality of channels; and after data arrangement in the first set of cache spaces for every channel is completed, writing data arranged in the first set of cache spaces for every channel to the FLASH memory via the plurality of channels.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: September 6, 2016
    Assignee: SILICON MOTION, INC.
    Inventors: Chang-Kai Cheng, Kuan-Yu Ke
  • Patent number: 9430168
    Abstract: A non-transitory computer-readable recording medium has stored therein a program for causing a computer to execute a process. The process includes identifying a data block from among a plurality of data blocks in a first storage for relocation to a second storage, determining an access mode of the identified data block, the access mode including sequential access or random access, and relocating the identified data block to the second storage based on the determined access mode.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: August 30, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Tomoaki Abe
  • Patent number: 9418009
    Abstract: A processor may include a memory controller to interface with a system memory having a near memory and a far memory. The processor may include logic circuitry to cause memory controller to determine whether a write request is generated remotely or locally, and when the write request is generated remotely to instruct the memory controller to perform a read of near memory before performing a write, when the write request is generated locally and a cache line targeted by the write request is in the inclusive state to instruct the memory controller to perform the write without performing a read of near memory, and when the write request is generated locally and the cache line targeted by the write request is in the non-inclusive state to instruct the memory controller to read near memory before performing the write.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Adrian C. Moga, Vedaraman Geetha, Bahaa Fahim, Robert G. Blankenship, Yen-Cheng Liu, Jeffrey D. Chamberlain, Stephen R. Van Doren
  • Patent number: 9400742
    Abstract: A storage control device of an outboard motor writing operation history information of the outboard motor to a nonvolatile memory by using an electric power generated by driving of an internal combustion engine, the storage control device includes a stop instruction detecting unit detecting a stop instruction of the driving of the internal combustion engine by a boat operator, a writing unit writing the operation history information to the nonvolatile memory in accordance with the stop instruction detected by the stop instruction detecting unit, a write judgment unit judging whether or not the operation history information is written to the nonvolatile memory by the writing unit, and a stop processing unit stopping the driving of the internal combustion engine after it is judged that the operation history information is written to the nonvolatile memory by the write judgment unit.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: July 26, 2016
    Assignee: SUZUKI MOTOR CORPORATION
    Inventor: Tomohiko Miyaki