Patents Examined by Sanjiv Shah
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Patent number: 11609717Abstract: A distributed computing environment is provided with a system and method for supporting rare copy-on-write data access. The system operates a data structure in a read only pattern suitable for serving a plurality of read requests with reduced overhead. The system, upon receiving a write request, creates a copy of data to execute the write request. The system defers writing the mutated data back to the read-only data structure. The system thus allows for multiple mutations to be made to the copy of the data using a read/write access pattern. After a number of read-only requests are received, the mutated data is written back to the read-only data structure. A monitor counts read and write requests in order to reduce overall read/write overhead and enhance performance of the distributed data grid.Type: GrantFiled: October 5, 2021Date of Patent: March 21, 2023Assignee: ORACLE INTERNATIONAL CORPORATIONInventor: Mark Falco
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Patent number: 11599286Abstract: A method includes determining respective valid translation unit counts of a block of non-volatile memory cells over a period of time, determining a rate of change of the respective valid translation unit counts of the block of non-volatile memory cells over the period of time, comparing the rate of change of the valid translation unit counts to a bin transition rate, and based on comparing the rate of change of the valid translation unit counts to the bin transition rate, performing a media management operation on the block of non-volatile memory cells.Type: GrantFiled: June 3, 2021Date of Patent: March 7, 2023Assignee: Micron Technology, Inc.Inventors: Ashutosh Malshe, Vamsi Pavan Rayaprolu, Kishore K. Muchherla
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Patent number: 11599300Abstract: A method includes performing a first read operation involving a set of memory cells using a first voltage, determining a quantity of bits associated with the set of memory cells based on the first read operation, performing a second read operation involving the set of memory cells using a second voltage that is greater than the first voltage when the quantity of bits is above a threshold quantity of bits for the set of memory cells, and performing the second read operation involving the set of memory cells using a third voltage that is less than the first voltage when the quantity of bits is below the threshold quantity of bits for the set of memory cells.Type: GrantFiled: April 19, 2021Date of Patent: March 7, 2023Assignee: Micron Technology, Inc.Inventors: Chun Sum Yeung, Guang Hu, Ting Luo, Tao Liu
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Patent number: 11580030Abstract: Devices, systems, and methods are provided that cause a controller to receive a first command to read or write first data from or to a first logical address; and determine a first mapped logical address that the first logical address is mapped to. A first plurality of logical addresses is mapped to the first mapped logical address and includes the first logical address. The controller reads a first data structure at the first mapped logical address. The first data structure includes a pointer to a first intermediate physical address. The controller reads a second data structure at the first intermediate physical address. The second data structure includes a plurality of pointers to target physical addresses. The plurality of pointers includes a pointer to a first target physical address for the first logical address. The controller reads or writes the first data from or to the first target physical address.Type: GrantFiled: August 18, 2020Date of Patent: February 14, 2023Assignee: SMART IOPS, INC.Inventors: Ashutosh Kumar Das, Manuel Antonio d'Abreu
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Patent number: 11573720Abstract: A includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to: initialize a block family associated with the memory device; initialize a timer at initialization of the block family; and aggregate temperature values received from sensor(s) of the memory device over time to generate an aggregate temperature. Responsive to programming a page residing on the memory device, the processing device associates the page with the block family. The processing device closes the block family in response to the aggregate temperature being greater than a first temperature value and the timer reaching a first time value. The processing device closes the block family in response to the aggregate temperature being less than or equal to the first temperature value and the timer reaching a second time value that is greater than the first time value.Type: GrantFiled: August 19, 2020Date of Patent: February 7, 2023Assignee: Micron Technology, Inc.Inventors: Michael Sheperek, Larry J. Koudele, Bruce A. Liikanen, Steven Michael Kientz, Kishore Kumar Muchherla
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Patent number: 11550723Abstract: An apparatus, method, and system for memory bandwidth aware data prefetching is presented. The method may comprise monitoring a number of request responses received in an interval at a current prefetch request generation rate, comparing the number of request responses received in the interval to at least a first threshold, and adjusting the current prefetch request generation rate to an updated prefetch request generation rate by selecting the updated prefetch request generation rate from a plurality of prefetch request generation rates, based on the comparison. The request responses may be NACK or RETRY responses. The method may further comprise either retaining a current prefetch request generation rate or selecting a maximum prefetch request generation rate as the updated prefetch request generation rate in response to an indication that prefetching is accurate.Type: GrantFiled: August 27, 2018Date of Patent: January 10, 2023Assignee: Qualcomm IncorporatedInventors: Niket Choudhary, David Scott Ray, Thomas Philip Speier, Eric Robinson, Harold Wade Cain, III, Nikhil Narendradev Sharma, Joseph Gerald McDonald, Brian Michael Stempel, Garrett Michael Drapala
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Patent number: 11550727Abstract: Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.Type: GrantFiled: June 18, 2020Date of Patent: January 10, 2023Assignee: MICRON TECHNOLOGY, INC.Inventor: Amit Bhardwaj
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Patent number: 11500578Abstract: A method includes determining respective memory access counts of a plurality of blocks of non-volatile memory cells that are grouped into a plurality of respective groups, comparing the respective memory access counts to respective memory access thresholds, determining a respective memory access count of a block of non-volatile memory cells exceeds a respective memory access threshold, and performing a media scan operation on the block of non-volatile memory cells.Type: GrantFiled: April 19, 2021Date of Patent: November 15, 2022Assignee: Micron Technology, Inc.Inventor: Guang Hu
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Patent number: 11487475Abstract: A control method is applied to a flash memory controller, which includes the following steps: creating a write time table, wherein the write time table records block numbers of blocks having data stored therein and corresponding first time and second time; referring to the write time table to determine whether there is at least one first block in the flash memory module whose first time is earlier than a first threshold, and if so, recording the at least one first block into an expired block table; referring to the write time table to determine whether there is at least one second block in the flash memory module whose second time is earlier than a second threshold, and if so, recording the at least one second block into the expired block table; and referring to the expired block table to perform an expired block recycling operation.Type: GrantFiled: February 24, 2021Date of Patent: November 1, 2022Assignee: Silicon Motion, Inc.Inventor: Ching-Hui Lin
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Patent number: 11442632Abstract: This application relates to load balancing for a number of partitions of a network-based storage service. Each partition includes a number of server devices and/or network devices located in a data center and configured to provide access to storage resources hosted within the data center. User accounts are assigned to a particular partition such that requests related to a particular user account are routed to that partition. Periodically, a load balancing algorithm is executed to re-assign user accounts to different partitions to rebalance resource consumption across the different partitions. The load balancing algorithm can balance resource consumption for any number of resource types by generating a vector of resource utilization parameters for each user account, sorting the plurality of user accounts into clusters based on the vectors, and mapping at least some user accounts to different partitions.Type: GrantFiled: September 20, 2018Date of Patent: September 13, 2022Assignee: Apple Inc.Inventors: Nicolas A. Favre-Felix, Alexander Shraer, Ori Herrnstadt, Nathan L. Williams
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Patent number: 11442760Abstract: A processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. The execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. Other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.Type: GrantFiled: July 1, 2016Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Barry E. Huntley, Jr-Shian Tsai, Gilbert Neiger, Rajesh M. Sankaran, Mesut A. Ergin, Ravi L. Sahita, Andrew J. Herdrich, Wei Wang
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Patent number: 11436153Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device is comprised of a controller, a random access memory (RAM) unit, and a NVM unit, wherein the NVM unit is comprised of a plurality of zones. The RAM unit comprises a first logical to physical address table and the NVM unit comprises a second logical to physical address table. The zones are partitioned into sections, and each partitioned section aligns with a change log table. Data is written to each zone sequentially, and only one partitioned section is updated at a time for each zone. Each time a zone is erased or written to in the NVM unit, the first logical to physical address table is updated and the second logical to physical address table is periodically updated to match the first logical to physical address table.Type: GrantFiled: May 26, 2020Date of Patent: September 6, 2022Assignee: Western Digital Technologies, Inc.Inventors: Daniel L. Helmick, Mark Dancho, Ryan R. Jones
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Patent number: 11429279Abstract: A storage device is disclosed. The storage device may include storage for data. A host interface logic may receive a dataset and a logical address from a host. A stream assignment logic may assign a stream identifier (ID) to a compressed dataset based on a compression characteristic of the compressed dataset. The stream ID may be one of at least two stream IDs; the compressed dataset may be determined based on the dataset. A logical-to-physical translation layer may map the logical address to a physical address in the storage. A controller may store the compressed dataset at the physical address using the stream ID.Type: GrantFiled: December 11, 2020Date of Patent: August 30, 2022Inventors: Jingpei Yang, Jing Yang, Rekha Pitchumani
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Patent number: 11403215Abstract: A method of initializing a data storage system (DSS) is provided. The method includes (a) in response to the DSS booting, reading data from a first plurality of disks marked as part of a raw mirror which mirrors configuration data of the DSS between the first plurality of disks; (b) comparing sequence numbers from the read data read and selecting data from a disk of the first plurality having a latest sequence number; (c) obtaining configuration data of the DSS from the selected data; (d) using the configuration data to construct a topology of the DSS which includes information describing a relationship between a second plurality of disks of the DSS, RAID groups of the DSS, and logical disks presented to users, the second plurality of disks being larger than and including the first plurality of disks; and (e) initializing the RAID groups and the logical disks described by the topology based on the information of the topology.Type: GrantFiled: April 7, 2020Date of Patent: August 2, 2022Assignee: EMC IP Holding Company, LLPInventors: Hongpo Gao, Ree Sun, Huadong Li, Wayne Li, Jibing Dong, Shaoqin Gong
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Patent number: 11372554Abstract: A method, computer program product, and computing system for receiving one or more IO requests at a cache system for storing content in a storage array. A maximum number of concurrent backend IO requests may be associated with the storage array based upon, at least in part, a change in size of the storage array. The one or more TO requests may be flushed to the storage array via one or more backend IO requests from the cache system based upon, at least in part, the maximum number of concurrent backend IO requests associated with the storage array.Type: GrantFiled: July 27, 2017Date of Patent: June 28, 2022Assignee: EMC IP HOLDING COMPANY, LLCInventors: Changyu Feng, Henry Austin Spang, IV, Jian Gao, Xinlei Xu, Ruiyong Jia, Yousheng Liu
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Patent number: 11360856Abstract: Generally described, one or more aspects of the present application relate to a public snapshot service for creating and managing block-level snapshots on a cloud provider network. Storage locations for each block that comprise the snapshot can be enumerated on a snapshot manifest. Identification of storage location for a requested snapshot block can be improved using a manifest index.Type: GrantFiled: September 27, 2019Date of Patent: June 14, 2022Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Sandeep Kumar, Shobha Agrawal, Sahil Doshi, Suresh Babu Sajja
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Patent number: 11347647Abstract: Example storage systems, file system interfaces, and methods provide cache commit timing management for aggregated writes. A system includes a data cache configured to aggregate data requests in buffer segments. A cache manager determines a delay threshold for each buffer based on usage values of the data cache. The cache manager monitors a commit time value, determines when the commit time value satisfies the delay threshold, and moves aggregate data elements from the buffer to persistent storage.Type: GrantFiled: December 18, 2018Date of Patent: May 31, 2022Assignee: Western Digital Technologies, Inc.Inventor: Bruno Keymolen
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Patent number: 11314413Abstract: A tool for adjusting available physical tape storage capacities. The tool determines an initial capacity size for one or more tapes, wherein the initial capacity size is a maximum physical storage capacity provided by the one or more tapes. The tool assigns the one or more tapes to a logical cluster based, at least in part, on the initial capacity size for the one or more tapes. The tool determines an initial storage capacity for the one or more tapes, wherein the initial storage capacity is a starting logical storage capacity that is less than the maximum physical storage capacity provided by the one or more tapes. The tool determines an incremental growth threshold for the one or more tapes. Responsive to a determination that the incremental growth threshold is exceeded, the tool increments a logical storage capacity of the one or more tapes by an incremental growth assignment.Type: GrantFiled: April 12, 2016Date of Patent: April 26, 2022Assignee: International Business Machines CorporationInventors: David A. Brettell, Alan J. Fisher, Duke A. Lee, Alexander Nieves
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Patent number: 11294806Abstract: The disclosed embodiments provide a method, apparatus, and system for selecting, based on feedback from previous garbage collections, a portion of a referenced memory area for garbage collection within a time window. During the execution of a software program, the system selects a given portion of a referenced memory area on which garbage collection can be completed within the given time window and attempts to complete garbage collection on at least the given portion of the referenced memory area before the end of the given time window. Next, the system selects, based on the results of the garbage collection performed during the given time window, a subsequent portion of the referenced memory area on which garbage collection can be completed within the subsequent time window and attempts to complete garbage collection on at least the subsequent portion of the referenced memory area before the end of the subsequent time window.Type: GrantFiled: July 30, 2019Date of Patent: April 5, 2022Assignee: Oracle International CorporationInventors: Thomas Schatzl, Nils Mikael Gerdin, Erik Gustav Helin
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Patent number: 11249914Abstract: An in-memory cache for a computer system having a first storage and a second storage where the first storage is a cache for the second storage, tracks priority levels of block attributes stored therein. If a data item is cached in the first storage, the block attribute corresponding to the data item is stored in the in-memory cache as a high priority block attribute. If a data item evicted from the first storage, the block attribute corresponding to the data item is stored in the in-memory cache as a low priority block attribute. When the cache becomes full, the low priority block attributes are evicted before the high priority block attributes.Type: GrantFiled: April 12, 2016Date of Patent: February 15, 2022Assignee: VMware, Inc.Inventors: Wenguang Wang, Enning Xiang