Abstract: Physical storage devices are configured as a redundant array of independent disks (RAID). As such, storage space of the physical storage devices is allocated to the RAID, and each physical storage device is part of the RAID. Where a portion of the storage space of the physical storage devices is not allocated to the RAID, this portion of the storage space from a mixed drive capacity is configured so that it is usable and is not wasted.

Abstract: A memory system of one embodiment includes: a nonvolatile memory including a plurality of word lines each connected to memory cells, each one of the memory cells being capable storing two bits, the memory cells connected to one of the plurality of word lines constituting an upper page and a lower page, each one of the pages being a unit of data programming; a random access memory configured to store an address translation table indicating relationships between logical addresses designated by a host and physical addresses in the nonvolatile memory. The memory system of the embodiment further includes a memory controller which execute data fixing for saving the address translation table from the random access memory to the nonvolatile memory; and write dummy data to at least one page subsequent to the page in which valid data has been written in the nonvolatile memory before executing the data fixing.

Abstract: Mobile computing devices may be configured to compile and execute portions of a general purpose software application in an auxiliary processor (e.g., a DSP) of a multiprocessor system by reading and writing information to a shared memory. A first process (P1) on the applications processor may request address negotiation with a second process (P2) on the auxiliary processor, obtain a first address map from a first operating system, and send the first address map to the auxiliary processor. The second process (P2) may receive the first address map, obtain a second address map from a second operating system, identify matching addresses in the first and second address maps, store the matching addresses as common virtual addresses, and send the common virtual addresses back to the applications processor. The first and second processes (i.e., P1 and P2) may each use the common virtual addresses to map physical pages to the memory.

Abstract: A device can include an interface circuit configured to translate memory access requests at a controller interface of the interface circuit into signals at a memory device interface of the interface circuit that is different from the controller interface, the interface circuit including a write buffer memory configured to store a predetermined number of data values received at a write input of the controller interface, and a read buffer memory configured to mirror a predetermined number of data values stored in the write buffer memory; wherein the memory device interface comprises an address output configured to transmit address values, a write data output configured to transmit write data on rising and falling edges of a periodic signal, and a read data input configured to receive read data at the same rate as the write data.

Abstract: Methods and apparatus are provided for detection and decoding in flash memories using a correlation of neighboring bits or errors in neighboring bits. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in one or more pages of the flash memory device; converting the one or more read values for the plurality of bits to a reliability value, such as a log likelihood ratio (LLR), for a given bit among said plurality of bits based on a probability that a data pattern was written to the plurality of bits given that a particular pattern was read from the plurality of bits; and decoding the given bit in a given page of the one or more pages using the reliability value. The probability may be obtained from one or more transition probability tables, or may be based on one or more reference cells, prior decoded decisions or performance factors.

Abstract: The disclosure is related to systems and methods of managing data storage in a memory device. In a particular embodiment, a method is disclosed that includes receiving, in a data storage device, at least one data packet that has a size that is different from an allocated storage capacity of at least one physical destination location on a data storage medium in the data storage device for the at least one data packet. The method also includes storing the at least one received data packet in a non-volatile cache memory prior to transferring the at least one received data packet to the at least one physical destination location.

Abstract: An apparatus and method for processing unit reclaiming requests in a solid state memory device. The present invention provides a method of managing a memory which includes a set of units. The method includes selecting a unit from the set of units having plurality of subunits. The method further includes determining a number of valid subunits m to be relocated from the units selected for a batch operation where m is at least 2. The selecting is carried out by a unit reclaiming process.

Abstract: A storage device including a copy processor that carries out a copying process of storing the copy of the data stored in the copy-source volume into the copy-destination volume; a copying manager that prepares copying related to the copying process and sets the copying process to a stand-by state; an activation manager that sets activation target data representing a target to be activated for the copying process in response to an activation instruction from a superior device; and a copy controller that cancels the stand-by state of the copying process, being set the activation target data for, and causes the copy processor to carry out the copying process. This configuration makes it possible to back up data of multiple copy sessions, ensuring integrity in timing of data to be backed up without lowering the capability of an I/O process.

Abstract: A nonvolatile memory (“NVM”) buffer is incorporated into an NVM system between a volatile memory buffer and an NVM to decrease the size of the volatile memory buffer and organize data for programming to the NVM. Heterogeneous data paths may be are used for write and read operations such that the nonvolatile memory buffer is used only in certain situations.

Abstract: A memory device, a memory system, and operating methods thereof are provided. The method of operating the memory device, which includes a first memory cell and a second memory cell neighboring the first memory cell, includes counting a disturbance value of the second memory cell each time the first memory cell is accessed, updating a disturbance count value of the second memory cell based on the counting, adjusting a refresh schedule based on the disturbance count value of the second memory cell, a desired threshold and a maximum disturbance count value, and resetting the disturbance count value of the second memory cell and the maximum disturbance count value when the second memory cell is refreshed according to the adjusted refresh schedule.

Abstract: A semiconductor memory device includes a memory which comprises a confidential information area storing confidential information and a flag. A controller reads the flag from the memory when instructed to erase or write data in the confidential information area, determines whether the flag is set, erases or writes data in the confidential information area when the flag is clear, and abandons a process requested by an erase or write instruction when the flag is set. An authenticator uses data in the confidential information area to execute an operation for authentication. A management information area may store management information for associated pages. The flag may include a bit string and a complementary bit string to improve reliability of the flag. The confidential information area may store dummy data when the memory is used for uses other than an application with an authentication function, so no problem arises using a normal controller.

Abstract: Managing buffers in a hybrid system, in one aspect, may comprise selecting a first buffer management method from a plurality of buffer management methods; capturing statistics associated with access to the buffer in the hybrid system running under the initial buffer management method; analyzing the captured statistics; identifying a second buffer management method based on the analyzed captured statistics; determining whether the second buffer management method is more optimal than the first buffer management method; in response to determining that the second buffer management method is more optimal than the first buffer management method, invoking the second buffer management method; and repeating the capturing, the analyzing, the identifying and the determining.

Abstract: Some embodiments include an apparatus and a computer program product configured to re-align two-dimensional compressed data sets while preserving compression of the data. A set of one or more shifts and a corresponding set of one or more first dimension indices into a two-dimensional compressed data set for re-aligning the two-dimensional compressed data set are determined. Impact of re-aligning upon each vector in the second dimension of the two-dimensional compressed data set is determined while the two-dimensional compressed data set remains compressed. New compressed vectors are created in the second dimension resulting from re-aligning. Compression information is modified for each of the original vectors of the two-dimensional compressed data set that remain after re-aligning based, at least in part, on the new compressed vectors.

Abstract: Systems and methods for initializing a memory system are provided. One system includes a processor and a memory including a storage volume coupled to the processor. The storage volume includes a first bitmap for tracking an initialization process for the storage volume and a second bitmap for tracking a copying process for the storage volume. A method includes performing, via the processor, an initialization process for the storage volume and tracking, via the processor utilizing the first bitmap, the initialization process. The method further includes performing, via the processor, a copying process for the storage volume prior to completing the initialization process and tracking, via the processor utilizing the second bitmap, the copying process. Also provided are computer storage mediums including computer program code for performing the above method.

Abstract: A storage system is dynamically reconfigured. The storage system includes storage pools that each include one or more storage disks. Storage pools to be expanded are determined as target storage pools. For the target storage pools, source storage disks to be moved into the target storage pools are determined from other storage pools than the target storage pools in the storage system. The source storage disks are migrated to the respective target storage pools.

Abstract: Embodiments are directed towards cloning files in a distributed file system. In response to a request to create file clones, a file cloning application can be employed to generate file clones based on a source file. The file cloning application can generate a new inode for each new file clone and at least one new shadow store. Data blocks from the source file can be transferred to the shadow store. The transferred data blocks can be replaced with reference blocks that point to the data blocks transferred to the shadow store. Likewise, additional reference blocks pointing to data blocks in the shadow store can be generated for the new file clone inodes. Further, the shadow store can maintain reference counters that track the number of reference blocks pointing to each shadow store block. Also, file clones can be generated based on a point-in-time snapshot of the source file.

Abstract: A non-volatile memory (NVM) includes a memory cell array of multi-level memory cells (MLC) arranged in physical pages. A programming method for the NVM includes; receiving first data and partitioning the first data according to a single bit page capacity of a physical page to generate partitioned first data, programming the partitioned first data as single-bit data to a plurality of physical pages, and receiving second data and programming the second data as multi-bit data to a selected physical page among the plurality of physical pages, wherein the second data is simultaneously programmed to the MLC of the selected physical page.

Abstract: Disclosed herein is a memory access control circuit including: a determination section adapted to determine whether a target requested by a first wraparound memory access request from a processor is stored in a prefetch buffer; a request generation section adapted to generate a second wraparound memory access request including the target if it is determined that the target is not stored in the prefetch buffer; and an address conversion section adapted to convert the start address of the first wraparound memory access request according to predetermined rules for use as a start address of the second wraparound memory access request.

Abstract: A flash memory system having unequal number of memory die and method for operation are disclosed. The memory system includes a plurality of flash memory die distributed unevenly among different control lines, such that there are an unequal number of die between control lines. A total physical capacity of the plurality of flash memory die is greater than a total logical capacity such that the memory system is over provisioned with physical capacity. A logical address splitter directs data received from a host system and associated with host logical block addresses such that each control line only receives data associated with predetermined host logical block address ranges and directs the data such that a ratio of physical capacity to logical capacity is equal among each of the control lines, regardless of the different number of die and associated different physical capacity per control line.

Abstract: A storage apparatus is provided, including a first storage unit; a load information obtaining unit that obtains load information for each of a plurality of portions defined by dividing the first storage unit; a portion identifying unit that identifies a candidate portion that is to be relocated in the first storage unit based on the load information; a determining unit that determines whether or not data in the candidate portion is allowed to be migrated to a second storage unit, the second storage unit having a performance value higher than a performance value of the first storage unit; an adder that adds the second storage unit, when the determining unit determines that the data in the candidate portion is not allowed to be migrated; and a relocation unit that migrates the data in the candidate portion from the first storage unit to the added second storage unit.