Patents Examined by Sarai E Butler
  • Patent number: 11853180
    Abstract: A process detection system for rack and server in rack is disclosed. In the system, a detection device performs a server process detection of L10 stage on servers in a rack, and performs a rack process detection of L11 stage; when the detection device detects that a server in the rack fails in a server process during the server process detection of L10 stage or that the rack fails in a rack process during the rack process detection of L11 stage, the server is repaired, or replaced by a backup server. Before the detection flow is performed continuously, the server process detection of L10 stage is performed on the repaired server, or the backup server not performing the server process detection of L10 stage yet, and then. The detection flow can be performed continuously on the backup server which has performed the server process detection of L10 stage.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: December 26, 2023
    Assignees: Inventec (Pudong) Technology, Corporation Inventec Corporation
    Inventors: Yuan Bai, Fu-Cheng Liu
  • Patent number: 11853152
    Abstract: A Fail Bit (FB) repair method includes: a bank to be repaired of a chip to be repaired is determined; first repair processing is performed on a first FB using a redundant circuit; a bit position of a second FB in each target repair bank is determined, and second repair processing is performed on the second FB; an unrepaired FB in each target repair bank is determined, and candidate repair combinations of the unrepaired FBs and a candidate combination count are determined; and if the candidate combination count is greater than a combination count threshold, a target repair position is determined, and repair processing is performed on the target repair position using a Redundant Word-Line (RWL), the target repair position being a position of an FB that maximally reduces the candidate combination count after repair processing.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: December 26, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yui-Lang Chen
  • Patent number: 11853149
    Abstract: Generating error event descriptions by receiving a set of error messages associated with an error event, generating a tokenization of at least one line of the set of error messages, providing the tokenization to an attention head according to a context of the tokenization, providing an output of the attention head as input to a generative model, generating a description of the error event according to the output, and providing the description to a user.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: December 26, 2023
    Assignee: International Business Machines Corporation
    Inventors: Anjali Shah, Jennifer A. Mallette, Salim Roukos
  • Patent number: 11847035
    Abstract: Methods and systems for testing a functionality of a code modification operation are described. In an example, a processor can include a processor pipeline comprising one or more execution units. The processor pipeline can execute a first thread. The processor pipeline can further execute a second thread concurrently with the execution of the first thread. The second thread can be executed to modify the first thread using a code modification operation. The processor can further include a test module configured to validate a functionality of the code modification operation based on a result of the modified first thread.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: December 19, 2023
    Assignee: International Business Machines Corporation
    Inventors: Charles Leverett Meissner, Elena Tsanko, Brenton Yiu, John Martin Ludden, Bryan G. Hickerson
  • Patent number: 11841777
    Abstract: The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: December 12, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Alberto Troia, Antonino Mondello
  • Patent number: 11841781
    Abstract: Systems and methods are described for a non-disruptive planned failover from a primary copy of data at a primary storage system to a mirror copy of the data at a cross-site secondary storage system. According to an example, a planned failover feature of a multi-site distributed storage system provides an order of operations such that a primary copy of a first data center continues to serve I/O operations until a mirror copy of a second data center is ready. This planned failover feature improves functionality and efficiency of the distributed storage system by providing non-disruptiveness during planned failover—even if various failures occur. The planned failover feature also includes a persistent fence to avoid serving I/O operations during a timing window when both primary data storage and secondary data storage are attempting to have a master role to serve I/O operations and this avoids a split-brain situation.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: December 12, 2023
    Assignee: NetApp, Inc.
    Inventors: Akhil Kaushik, Anoop Vijayan, Omprakash Khandelwal
  • Patent number: 11829188
    Abstract: In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: November 28, 2023
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SAS, STMicroelectronics (Grand Ouest) SAS
    Inventors: Loic Pallardy, Nicolas Anquet, Dragos Davidescu
  • Patent number: 11829226
    Abstract: To improve promptness of anomaly detection after occurrence of an event, provided is an anomaly detection apparatus including a processor that executes a program and a storage device that stores the program. The processor executes a correction process of applying a scale transformation to correct second predicted data in time-series first predicted data of a monitoring target, the second predicted data including data after occurrence time of a specific event, and a detection process of detecting an anomaly of the monitoring target based on the second predicted data corrected in the correction process and based on second measured data in time-series first measured data of the monitoring target, the second measured data including data after the occurrence time of the specific event.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: November 28, 2023
    Assignee: HITACHI, LTD.
    Inventors: Satish Kumar Jaiswal, Mineyoshi Masuda
  • Patent number: 11815988
    Abstract: A system according to an embodiment of the present disclosure automatically responds to event alarms or failures in IT management in real-time and its operation method. The system provides a management object system accumulating responses IT managers made in case of issues including the event alarms, and the failures, wherein data is used as a learning data that suggests response measures for the event alarms or the failures through a status collector, a controller, and a linker, wherein future event alarms or failures, the learning data suggests the responding measures for corresponding phenomenon to the IT managers through a response measure suggester, and wherein responses are automatically made with a responder, where the responder is an artificial intelligence function.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: November 14, 2023
    Assignee: Infranics America Corp.
    Inventors: Young Sun Song, Jee Yoon Song, Neung Mo Koo, Yi Hwan Jang
  • Patent number: 11803443
    Abstract: A storage apparatus includes a plurality of drives and has a parity group constituted by a plurality of drives. The storage apparatus stores a hash management table to manage hash values of a prescribed data unit of data of the drives constituting the parity group and a hash value of a prescribed data unit of data stored in another drive other than the drives constituting the parity group. A processor is configured to determine whether a same data unit as a data unit included in data stored in a replacement target drive exists in the other drive on a basis of the hash values, and copy the same data unit of the other drive to a replacement destination drive when the same data unit exists.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: October 31, 2023
    Assignee: HITACHI, LTD.
    Inventor: Shota Fujita
  • Patent number: 11797371
    Abstract: A method for determining a Fail Bit (FB) repair scheme includes: a bank to be repaired of a chip to be repaired is determined, the bank to be repaired including multiple target repair areas; initial repair processing is performed on an FB in each of the target repair areas using a redundant circuit; responsive to that a number of remaining Redundant Word Lines (RWLs) is greater than 0 and a number of remaining Redundant Bit Lines (RBLs) is greater than 0, a candidate repair sub-scheme for each target repair area is determined, and a candidate repair cost corresponding to each candidate repair sub-scheme is determined; and a target repair scheme for the bank to be repaired is determined according to respective candidate repair sub-schemes and candidate repair costs, where the target repair scheme corresponds to a minimum integrated repair cost.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: October 24, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yui-Lang Chen
  • Patent number: 11789829
    Abstract: Methods and systems are disclosed herein for managing software operations in a computer system. A software operation may include many tasks. The tasks may be grouped together based on the tasks' dependencies on output generated from other tasks. Each group of tasks may be placed in a block of a blockchain based on the dependencies. If the output of a block fails to pass a validation test, the tasks in each block may be undone in an organized order (e.g., starting with the most recently performed task and using the one or more rollback functions associated with each task), which may prevent problems that could occur when some asynchronous tasks complete and others fail. Use of the blockchain may allow the computer system to determine more precisely where an operation failed and may allow the computer system to determine more information about the failure.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: October 17, 2023
    Assignee: Capital One Services, LLC
    Inventors: Christian Bartram, Connor Cason, Yvette White
  • Patent number: 11789804
    Abstract: A method of identifying a root cause of a failure for a trace within a microservices-based application includes determining if a root span of the trace is an error span resulting in an error experienced by a user at a front end of the microservices-based application. If the root span of the trace is an error span, the method analyzes a plurality of spans comprising the trace to determine if the trace comprises at least one leaf error span. If the trace comprises a single leaf error span, the method attributes the root cause of the failure in the trace to a service associated with the single leaf error span. If the trace comprises multiple leaf error spans the method attributes the root cause of the failure in the trace to a service associated with a leaf error span of the multiple leaf error spans comprising a latest starting timestamp.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: October 17, 2023
    Assignee: SPLUNK Inc.
    Inventors: Gergely Danyi, Sakshi Garg, Maxime Petazzoni, Sahinaz Safari Sanjani, Timothy Matthew Robin Williamson, Eric Wohlstadter
  • Patent number: 11789842
    Abstract: Methods and systems for managing deployments are disclosed. A deployment may include one or more devices. The devices may include hardware and/or software components. The operation of the deployment may depend on the operation of these devices and components. To manage the operation of the deployment, a system may include a deployment manager. The deployment manager may obtain logs for components of the deployment reflecting the historical operation of these components and use the log to predict the future operation of the deployment. Based on the predictions, the deployment manager may take proactive action to reduce the likelihood of the deployment becoming impaired.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: October 17, 2023
    Assignee: Dell Products L.P.
    Inventors: Dale Wang, Min Gong, Ashok Narayanan Potti
  • Patent number: 11789808
    Abstract: A memory device includes a mode register set configured to store a first repair mode, a second repair mode, and a second repair off mode, and a repair control circuit configured to perform a first repair operation for permanently repairing a first wordline corresponding to a defective address to a first redundancy wordline in the first repair mode, to perform a second repair operation for temporarily repairing the first wordline corresponding to the defective address to a second redundancy wordline in the second repair mode, and to turn off a repair logic that is configured to perform the second repair operation in the second repair off mode to access old data after the second repair operation.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: October 17, 2023
    Inventor: Yongsang Park
  • Patent number: 11789809
    Abstract: Aspects of the present disclosure involve systems and methods for improving the performance of a telecommunications network by monitoring the performance of one or more storage drives. Operational data is received from a plurality of storage drives of a storage server of a telecommunications network. A plurality of operational coefficients for each of the plurality of storage drives is derived based on the operational data, and a cluster plot is created from the plurality of operational coefficients for each of the plurality of storage drives. A distance is calculated between a subset of operational coefficients of the plurality of operational coefficients of the cluster plot, and a remedial action is initiated on a storage drive of the plurality of storage drives when a calculated distance of an operational coefficient associated with the storage drive exceeds a distance value from a cluster of the cluster plot.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: October 17, 2023
    Assignee: Level 3 Communications, LLC
    Inventors: William Hopkins, Lawrence W. Gowin
  • Patent number: 11789807
    Abstract: Systems and methods are disclosed to provide an autonomous management of communication links between dice on a multi-die assembly. Each die can include a detection unit and a controller to detect a failing communication link and perform link maintenance by directing the communication traffic on the failing link to an operational link before the link fails. Once the failing link has been repaired, the controller can re-direct the traffic back to the repaired link. The controllers on each die can negotiate through a handshake process to provide the continuous operation by switching the communication traffic from the failing link to the operational link, and then from the operational link to the repaired link.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: October 17, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Gal Kochavi, Benny Pollak, Sergey Kleyman, Itai Avron
  • Patent number: 11789801
    Abstract: Systems and methods are described for improved error logging during system boot and shutdown. A hardware initialization firmware on a computing device can include a logging module. When errors occur during early system booting or late system shutdown, the firmware can create error logs. The logging module can receive the error logs and prioritize them according to a set of rules. The logging module can select error logs of the highest priority up to a predetermined maximum amount. The logging module can modify the error logs using a shorthand form and write them to nonvolatile random-access memory. The firmware can initialize runtime services and launch an operating system. A system logger on the operating system can retrieve the error logs, save them to a file, and erase them from the memory.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: October 17, 2023
    Assignee: VMware, Inc
    Inventors: Ashish Kaila, Tobias Stumpf, Mukund Gunti
  • Patent number: 11782631
    Abstract: An illustrative method includes receiving a write request to write payload data to a virtual storage volume; transmitting the write request to a plurality of storage nodes each storing a replica of the virtual storage volume; acknowledging the write request only after a quorum of the storage nodes has stored the payload in their respective kernel memory; and flushing the payloads stored in each kernel memory to persistent storage only after a threshold number of outstanding write requests that have been acknowledged, but not yet flushed, has been reached, the flushing configured to optimize performance for synchronous workloads.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: October 10, 2023
    Assignee: Pure Storage, Inc.
    Inventors: Vinod Jayaraman, Prabir Paul
  • Patent number: 11783209
    Abstract: Embodiments of the present invention provide a system for dynamically processing application service requests. The system is configured for receives an application service request from at least one channel, where the application service request is associated with an application of one or more applications associated with an entity, extracts one or more variants of standard operating procedure associated with the application service request, wherein the one or more variants are solutions associated with processing the application service request, determines, via an artificial intelligence engine, an optimal variant from the one or more variants to process the application service request, and implements one or more actions associated with the optimal variant to process the application service request.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: October 10, 2023
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Sasidhar Purushothaman, Vani Kodali, Ramadhar Singh, Pavan R. Talakanti