Abstract: A method of producing an oxide layer on a foil for use in a capacitor includes immersing the foil in a first solution; maintaining a target current between the immersed anodic foil and the first solution until a first target voltage is reached to form an oxide layer overlying the foil; maintaining the target current between the immersed foil and the first solution until a second target voltage is reached to reform the oxide layer; removing the foil from the first solution and heating the foil; immersing the heat treated foil in a second solution; maintaining the target current between the immersed foil and the second solution until a third target voltage is reached; and discharging the immersed foil after each of the first, second, and third target voltages are reached.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.

Abstract: A method including determining a type of structural asymmetry of the target from measured values of the target, and performing a simulation of optical measurement of the target to determine a value of an asymmetry parameter associated with the asymmetry type. A method including performing a simulation of optical measurement of a target to determine a value of an asymmetry parameter associated with a type of structural asymmetry of the target determined from measured values of the target, and analyzing a sensitivity of the asymmetry parameter to change in a target formation parameter associated with the target. A method including determining a structural asymmetry parameter of a target using a measured parameter of radiation diffracted by the target, and determining a property of a measurement beam of the target based on the structural asymmetry parameter that is least sensitive to change in a target formation parameter associated with the target.

Abstract: A sonar mapping system that includes a sonar transducer assembly configured for mounting on a watercraft, and a display configured to show a topographical chart of a body of water. The sonar mapping system further includes a processor coupled to the sonar transducer assembly and display. The processor is configured to create the topographical chart in real time, and to update the topographical chart in real time, based on sonar data provided by the sonar transducer assembly. The processor is also configured to render the created or updated topographical chart on the display. The sonar mapping system has memory accessible by the processor and configured to store the topographical chart rendered by the processor, and to store the sonar data provided by the sonar transducer assembly.

Abstract: A back-end-of-the-line (BEOL) metal-insulator-metal (MIM) capacitor is provided that includes three electrode plates in which the first electrode plate of the MIM capacitor is an electrically conductive interconnect structure embedded in a first interconnect dielectric material layer. The other two electrode plates are located in a second interconnect dielectric material layer that is located above the first interconnect dielectric material layer. A first contact structure is present in the second interconnect dielectric material layer and contacts a surface of the first interconnect dielectric material layer, wherein the first contact structure passes through the second electrode plate. A second contact structure is also present in the second interconnect dielectric material layer and contacts a surface of the first electrode plate, wherein the second contact structure passes through the third electrode plate. Capacitor dielectric materials are located between each of the electrode plates.

Abstract: A workpiece treating method includes a step (1) of forming a stack including a support, a temporary fixing material and a workpiece wherein the material includes a layer containing a polymer (A) in a range of not less than 50 mass %, the polymer (A) including a structural unit represented by the formula (A1), and the workpiece is held on the material; a step (2) of processing the workpiece and/or transporting the stack; and a step (3) of applying a shear force to the material to thereby separate the workpiece from the support. R1 is a divalent organic group including at least one aromatic ring, each of two oxygen atoms bonded to R1 in (A1) is bonded to the aromatic ring, and, when R1 includes two or more aromatic rings, each of the two oxygen atoms is bonded to any one of the aromatic rings.

Abstract: A process includes providing furan-2,5-dicarboxylic dimethyl ester (FDME), reacting the FDME with a Grignard reagent to form a bis-alkylketone furan having R groups selected from the group consisting of a C1-C20 linear alkyl chain, a C2-C24 branched alkyl chain, and a hydrogen atom. An additional process includes mixing a 3,4-dibrominated bis-alkylketone furan with potassium carbonate, and adding ethyl-mercaptoacetate to the mixture. This process also includes stirring the mixture to form a bis-alkyl-DTF diester fused ring structure, which is then brominated to form a dibromo-DTF compound.

Abstract: The present disclosure discloses a display panel, and the display panel includes: a first substrate and a second substrate; a plurality of first gate lines and a plurality of first data lines arranged on the first substrate, a plurality of second gate lines and a plurality of second data lines arranged on the second substrate, wherein a plurality of first pixel areas are defined by the plurality of first gate lines and the plurality of first data lines, and a plurality of second pixel areas are defined by the plurality of second gate lines and the plurality of second data lines; the projections of the portion of the plurality of first pixel areas with the first thin film transistors projected on the second substrate is located between at least two adjacent second pixel areas with the second thin film transistors.

Abstract: A supercapacitor according to the present invention includes a negative carbon-comprising electrode which does not intercalate sodium, and a positive carbon-comprising electrode. An electrolyte composition comprises sodium hexafluorophosphate and a non-aqueous solvent comprising at least one selected from the group consisting of ethylene glycol dimethyl ether, diethylene glycol dimethyl ether, triethylene glycol dimethyl ether, and tetraethylene glycol dimethyl ether. The supercapacitor has an electrochemical voltage window of from +0.0 V to 3.5 V (full cell voltage). The electrolyte has an electrochemical voltage window of from +0.05 V to 3.9 V vs. Na/Na+. A method of making and a method of operating a supercapacitor is also disclosed.

Abstract: Integrated circuit transistor structures are provided that may reduce capacitive parasitics by using metal on both sides (top and bottom) of a given integrated circuit transistor device layer. For example, in an embodiment, the drain metal interconnect is provided above the transistor device layer, and the source metal interconnect is provided below the transistor layer. Such a configuration reduces the parasitic capacitance not only between the source and drain metal interconnect layers, but also between the neighboring conductors of the drain metal interconnect layer, because the number of pass-thru conductors in the drain metal interconnect layer to access an upper conductor in the source metal interconnect layer is reduced. In other embodiments, the source metal interconnect remains above the transistor device layer, and the drain metal interconnect is moved to below the transistor device layer, to provide similar benefits. Techniques apply equally to any transistor type, including FETs and BJTs.

Abstract: A photodiode fabricated using spalling techniques, and method for making the same. The photodiode including a substrate, an optical device semiconductor material layer disposed over the substrate, a p-type contact disposed over the optical device semiconductor material layer, an n-type contact disposed over the substrate, and an adhesion layer for rear illumination adhered to the bottom of the substrate. Both the substrate and the optical device semiconductor material layer comprise at least one of GaN, AlGaN or AlN.

Abstract: Embodiments of an embedded mm-wave radio integrated circuit into a substrate of a phased array module are disclosed. In some embodiments, the phased array module includes a first set of substrate layers made of a first material. The mm-wave radio integrated circuit may be embedded in the first set of substrate layers. A second set of substrate layers may be coupled to the first set of substrate layers. The second set of substrate layers may be made of a second material that has a lower electrical loss than the first material. The second set of substrate layers may include a plurality of antenna elements coupled through vias to the mm-wave radio integrated circuit.

Abstract: An optical element is disclosed. In an embodiment an optical element includes a substrate having a silicone surface, an antireflection layer overlying the silicone surface, wherein the antireflection layer comprises a first organic layer having a reflection-reducing nanostructure, the nanostructure having a depth of at least 30 nm, and a cover layer overlying the first organic layer, the cover layer having a thickness of no more than 40 nm.

Abstract: A flexible thin film transistor and a method for fabricating the same are provided. The flexible thin film transistor has: a flexible substrate; an inorganic insulating layer disposed on the flexible substrate; and a thin film transistor disposed on the inorganic insulating layer. A rough structure is formed on a side surface of the inorganic insulating layer facing toward the thin film transistor.

Abstract: A semiconductor device includes a first electrode layer and a second electrode layer formed thereon to be spaced from the first electrode layer, a columnar portion penetrating the first and second electrode layers in a first direction and including a semiconductor layer, a first insulating film between the first and second electrode layers and the semiconductor layer and in contact with the first electrode layer, a charge storage layer between the second electrode layer and the first insulating film, and an insulating film between the second electrode layer and the charge storage layer. The semiconductor layer includes a first portion facing the second electrode layer in a second direction intersecting with the first direction and a second portion in contact with the first portion in the first direction. A concentration of a impurity contained in the second portion is higher than that of the impurity contained in the first portion.

Abstract: The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one Titanium (Ti) layer between multiple HK layers. A high-k/metal gate semiconductor device including at least one TiO2 layer between multiple HK layers is also provided.

Abstract: A well of a first conductivity type is insulated from a substrate of the same first conductivity type by a structure of a triple well type. The structure includes a trench having an electrically conductive central part enclosed in an insulating sheath. The trench supports a first electrode of a decoupling capacitor, with a second electrode provided by the well.

Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.

Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.

Abstract: A system for detecting a leak or spill and mitigating losses resulting therefrom comprises a floor covering and a software application. The floor covering includes a sensor assembly, a processing element, and a transmitter. The sensor assembly generates information when exposed to liquid. The processing element determines a location of the liquid based upon the information from the sensor assembly. The transmitter transmits data regarding the liquid. The software application executes on an electronic device and is operable to receive data from the floor covering regarding the liquid; display a message that liquid has been detected on the floor covering; calculate an area of the liquid; determine whether a leak is still occurring and if so, shut an electronically controllable valve; transmit data regarding the liquid to an insurance provider; and/or receive insurance-related information from the insurance provider, such as information related to a proposed insurance claim or estimated damage.