Abstract: A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other.

Abstract: An ESD protection device may include a substrate, a first conductivity region arranged at least partially within the substrate, a second conductivity region arranged at least partially within the first conductivity region, third and fourth conductivity regions arranged at least partially within the second conductivity region, and first and second terminal portions arranged at least partially within the third and fourth conductivity regions respectively. The third and fourth conductivity regions may be spaced apart from each other. The substrate and the second conductivity region may have a first conductivity type. The first conductivity region, third conductivity region, fourth conductivity region and first and second terminal portions may have a second conductivity type different from the first conductivity type. The first and second terminal portions may have higher doping concentrations than the third and fourth conductivity regions respectively.

Abstract: Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.

Abstract: A magnetoresistive device may include a first plurality of magnetic tunnel junction (MTJ) bits arranged in a first XY plane, and a second plurality of MTJ bits arranged in a second XY plane that is spaced apart from the first XY plane in a Z direction. And, the MTJ bits of the first plurality of MTJ bits may be spaced apart from the MTJ bits of the second plurality of MTJ bits in the X and Y directions.

Abstract: A semiconductor structure includes a transceiver, a molding surrounding the transceiver, and a RDL disposed over the transceiver. The RDL includes an antenna and a dielectric layer. The antenna is disposed over and electrically connected to the transceiver. The dielectric layer surrounds the antenna. The antenna includes an elongated portion and a via portion. The elongated portion extends over the molding, and the via portion is electrically connected to the transceiver.

Abstract: A package structure includes a substrate, a first capacitor, a System on Chip unit and a wiring layer. The first capacitor is provided on the substrate. The System on Chip unit is bonded with the first capacitor in a first dielectric layer. The wiring layer is configured to electrically couple the first capacitor and the System on Chip unit. The wiring layer is provided on the first dielectric layer through a second dielectric layer.

Abstract: In an embodiment, a FinFET device includes a semiconductor substrate and forming fins of a first height and a second height. A dielectric layer extends a fin of the first height to the fin of a second height. The dielectric layer is disposed on the top surface of the fin of the second height.

Abstract: An automated workpiece conveying vehicle included in a conveyance system that conveys a workpiece to each of a plurality of processing apparatuses is provided. The automated workpiece conveying vehicle includes: a workpiece support part that supports the workpiece; a traveling mechanism provided on the workpiece support part; a vibration detection unit that detects vibration of the workpiece support part and records the vibration as vibration data; and a receiver that receives a control signal transmitted from a control unit included in the conveyance system, the control signal instructing conveyance of the workpiece to the processing apparatus.

Abstract: A pressure sensor designed to detect a value of ambient pressure of the environment external to the pressure sensor includes: a first substrate having a buried cavity and a membrane suspended over the buried cavity; a second substrate having a recess, hermetically coupled to the first substrate so that the recess defines a sealed cavity the internal pressure value of which provides a pressure-reference value; and a channel formed at least in part in the first substrate and configured to arrange the buried cavity in communication with the environment external to the pressure sensor. The membrane undergoes deflection as a function of a difference of pressure between the pressure-reference value in the sealed cavity and the ambient-pressure value in the buried cavity.

Abstract: A method of forming an electrical device that includes forming a multilayered fin composed of a first source/drain layer for a first transistor, a first channel layer for the first transistor, a common source/drain layer for the first transistor and a second transistor, a second channel layer for the second transistor and a second source/drain layer for the second transistor. A common spacer is formed on the common source/drain layer that separates a first opening to the first channel layer from a second opening to the second channel layer. Gate structures are then formed in the first and second openings.

Abstract: Self-limiting cavities are formed within a crystalline semiconductor substrate and beneath a stack of semiconductor layers used to form a nanosheet transistor device. Inner ends of the cavities merge beneath the stack while the outer ends thereof adjoin isolation regions within the substrate. The cavities are filled with electrically insulating material to provide bottom device isolation. Source/drain regions are grown in vertical trenches extending through the stack of semiconductor layers following formation of dielectric inner spacers. The bottom ends of the trenches adjoin the electrically insulating material within the cavities.

Abstract: Provided are a laser machining device and a laser machining method capable of stably operating an autofocus function without causing an unfavorable state such as an overshoot etc. A laser machining device and a laser machining method of the present invention performs a normal AF (autofocus) control when a scan position of the machining laser light and the detecting laser light is located in a work central portion, and performs a slow-tracking AF (autofocus) control with a trackability to a displacement of a main surface of a work reduced to be lower than a trackability of the normal AF control when the scan position of the machining laser light and the detecting laser light is located in a work end portion.

Abstract: There are two parts to build fusion carbon metal interconnects. First are the fusing metals/alloys, typically in the Martensite phase and lacking carbon. Second are carbonized materials that have carbon infused. These carbonized materials may be referred to as carbon donating materials. Both parts can be interchanged as the substrate or mounted component, or the parts can form linear interface connections. The finished interfaces have very low electrical resistance and/or zero interface electrical resistance. The interconnect circuit topography materials and connections are endless and is dependent on circuit design. One example of such interface is a solderless thermoelectric device capable of use at higher operating temperatures as compared to conventional low temperature solders thus allowing the thermoelectric device to be used in a Seebeck device, for example. The thermoelectric device forms a fusion layer between a copper metal layer and a semiconductor wafer layer to create a true metallurgical bond.

Abstract: Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide layer on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide layer in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer. In another embodiment, a method includes supplying a deposition gas mixture including at least a metal containing precursor and a reacting gas on a surface of a substrate, forming a plasma in the presence of the deposition gas mixture by exposure to microwave power, exposing the plasma to light radiation, and forming a metal silicide layer on the substrate from the deposition gas.

Abstract: High-frequency supercapacitors that can respond at kilohertz frequencies (AC-supercapacitors). The electrodes of the AC-supercapacitors include edge oriented graphene (EOG) electrodes or carbon nanofiber network (CNN) electrodes. The EOG electrodes are formed by utilizing a plasma and feedstock carbon gas to carbonize cellulous paper and deposit graphene implemented in one step. The CNN electrodes are formed by pyrolyzing a carbon nanofiber network utilizing a plasma.

Abstract: Processes are provided herein for deposition of organic films. Organic films can be deposited, including selective deposition on one surface of a substrate relative to a second surface of the substrate. For example, polymer films may be selectively deposited on a first metallic surface relative to a second dielectric surface. Selectivity, as measured by relative thicknesses on the different layers, of above about 50% or even about 90% is achieved. The selectively deposited organic film may be subjected to an etch process to render the process completely selective. Processes are also provided for particular organic film materials, independent of selectivity. Masking applications employing selective organic films are provided. Post-deposition modification of the organic films, such as metallic infiltration and/or carbon removal, is also disclosed.

Abstract: A mask-integrated surface protective film, containing: a substrate film, and a mask material layer provided on the substrate film; wherein the mask material layer is an ethylene-vinyl acetate copolymer resin, an ethylene-methyl acrylate copolymer resin, or an ethylene-butyl acrylate copolymer resin; and wherein the thickness of the mask material layer is 50 ?m or less.

Abstract: The present invention relates to novel phosphor mixtures and to a light-emitting device which comprises at least one of the novel phosphor mixtures. The phosphor mixtures can be used in phosphor-converted LEDs with a semiconductor that emits in the violet spectral region. The present invention furthermore relates to a lighting system which may comprise the light-emitting devices according to the invention, and to a dynamic lighting system. The present invention furthermore relates to a process for the preparation of the phosphor mixtures according to the invention and to the use thereof in light-emitting devices for use in general lighting and/or in specialty lighting.

Abstract: A semiconductor device includes a substrate, an active region and an inactive region surrounding the active region, a gate electrode, a drain electrode and a source electrode on the active region, a drain interconnection including a drain finger and a drain bar, and a source interconnection including a source finger and a source bar. The source bar is located on an opposite side of the drain bar across the active region in a first direction. The source electrode includes a first side facing the drain bar in the first direction and a first depression in a middle of the first side. A first depth of the first depression in the first direction is equal or more than a first interval between the drain bar and the first side in the first direction.

Abstract: A sensor including a layer of amorphous selenium (a-Se) and at least one charge blocking layer is formed by depositing the charge blocking layer over a substrate prior to depositing the amorphous selenium, enabling the charge blocking layer to be formed at elevated temperatures. Such a process is not limited by the crystallization temperature of a-Se, resulting in the formation of an efficient charge blocking layer, which enables improved signal amplification of the resulting device. The sensor can be fabricated by forming first and second amorphous selenium layers over separate substrates, and then fusing the a-Se layers at a relatively low temperature.