Patents Examined by Sean E Vincent
  • Patent number: RE47529
    Abstract: An Fe-base in-situ composite alloy, castable into 3-dimensional bulk objects is provided, where the alloy includes a matrix having one or both of a nano-crystalline phase and an amorphous phase, and a face-centered cubic crystalline phase. The alloy has an Fe content of more than 60 atomic percent.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: July 23, 2019
    Assignee: Apple Inc.
    Inventors: William L. Johnson, Choongnyun Paul Kim
  • Patent number: RE47544
    Abstract: Provided are a method of manufacturing an organic light emitting display device and an organic light emitting display device manufactured by the method. The method includes calculating a peak-luminance current density for each of a red sub-pixel, a blue sub-pixel, a green sub-pixel, and a white sub-pixel, calculating an average use current density for each of the red sub-pixel, blue sub-pixel, green sub-pixel, and white sub-pixel; determining a size of each sub-pixel with the peak-luminance current density and the average use current density, and forming the sub-pixels with the determined sizes of the respective sub-pixels. The present invention sets the size of each sub-pixel in consideration of a peak-luminance current density and an average use current density, thus easily achieving the peak luminance and enhancing the color-coordinate life.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 30, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Hwa Kyung Kim, Byung Chul Ahn, Chang Wook Han, Woo Jin Nam, Hong Seok Choi, Yoon Heung Tak, Shinji Takasugi
  • Patent number: RE47562
    Abstract: A method for controlling IC device strain and the devices thereby formed are disclosed. An exemplary embodiment includes receiving an IC device substrate having a device region corresponding to an IC device. An implantation process is performed on the device region forming an amorphous region within the device region. The IC device substrate is recessed to define a source/drain recess in the device region having a profile determined by the amorphous structure of the amorphous region. A source/drain epitaxy is then performed to form a source/drain structure within the source/drain recess.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Fai Cheng, Bwo-Ning Chen, Chin-Te Su, Huang-Sheng Ho
  • Patent number: RE47709
    Abstract: A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILD layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Chun Hsieh, Wei-Cheng Wu, Hsiao-Tsung Yen, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: RE47863
    Abstract: The present invention relates to novel non-ferromagnetic amorphous steel alloys represented by the general formula: Fe—Mn-(Q)-B-M, wherein Q represents one or more elements selected from the group consisting of Sc, Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu, and M represents one or more elements selected from the group consisting of Cr, Co, Mo, C and Si. Typically the atomic percentage of the Q constituent is 10 or less. An aspect is to utilize these amorphous steels as coatings, rather than strictly bulk structural applications. In this fashion any structural metal alloy can be coated by various technologies by these alloys for protection from the environment. The resultant structures can utilize surface and bulk properties of the amorphous alloy.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: February 18, 2020
    Assignee: University of Virginia Patent Foundation
    Inventors: Gary J. Shiflet, S. Joseph Poon, Xiaofeng Gu
  • Patent number: RE48111
    Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: July 21, 2020
    Assignee: JCET Semiconductor (Shaoxing) Co. Ltd.
    Inventors: Reza A. Pagaila, Seng Guan Chow, Seung Uk Yoon, Byung Tai Do, Linda Pei Ee Chua
  • Patent number: RE48202
    Abstract: The electric device (1, 100) has a body (2, 101) with a resistor (7, 250) comprising a phase change material being changeable between a first phase and a second phase. The resistor (7, 250) has an electric resistance which depends on whether the phase change material is in the first phase or the second phase. The resistor (7, 250) is able to conduct a current for enabling a transition from the first phase to the second phase. The phase change material is a fast growth material which may be a composition of formula Sb1?cMc with c satisfying 0.05?c?0.61, and M being one or more elements selected from the group of Ge, In, Ag, Ga, Te, Zn and Sn, or a composition of formula SbaTebX100?(a+b) with a, b and 100?(a+b) denoting atomic percentages satisfying 1?a/b?8 and 4?100?(a+b)?22, and X being one or more elements selected from Ge, In, Ag, Ga and Zn.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: September 8, 2020
    Assignee: III Holdings 6, LLC
    Inventors: Martijn Henri Richard Lankhorst, Liesbeth Van Pieterson, Robertus Adrianus Maria Wolters, Erwin Rinaldo Meinders
  • Patent number: RE48378
    Abstract: In a crystal growth apparatus and method, polycrystalline source material and a seed crystal are introduced into a growth ambient comprised of a growth crucible disposed inside of a furnace chamber. In the presence of a first sublimation growth pressure, a single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a first gas that includes a reactive component that reacts with and removes donor and/or acceptor background impurities from the growth ambient during said sublimation growth. Then, in the presence of a second sublimation growth pressure, the single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a second gas that includes dopant vapors, but which does not include the reactive component.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: January 5, 2021
    Assignee: II-VI Delaware, Inc.
    Inventors: Ilya Zwieback, Ping Wu, Varatharajan Rengarajan, Avinash K. Gupta, Thomas E. Anderson, Gary E. Ruland, Andrew E. Souzis, Xueping Xu
  • Patent number: RE48408
    Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: January 26, 2021
    Inventors: Reza A. Pagaila, Seng Guan Chow, Seung UK Yoon, Byung Tai Do, Linda Pei Ee Chua
  • Patent number: RE48877
    Abstract: A multi-layer ceramic capacitor has a structure where the dispersion, nd, of average grain size of the dielectric grains constituting the dielectric layer (a value (D90/D10) obtained by dividing D90 which is a grain size including 90% cumulative abundance of grains by D10 which is a grain size including 10% cumulative abundance of grains) is smaller than 4.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Koichiro Morita, Tetsuo Shimura
  • Patent number: RE48990
    Abstract: A liquid ejection apparatus and method of manufacture are disclosed. One apparatus includes a pressure chamber, a diaphragm covering the pressure chamber, and a piezoelectric element having a piezoelectric component positioned opposing the pressure chamber. The apparatus further includes a first electrode disposed on a first side of the piezoelectric component toward the pressure chamber and a second electrode disposed on a second side of the piezoelectric component opposite the first side in an opposed region, the opposed region being a region opposed to the second electrode. The apparatus also includes a metal film disposed between the piezoelectric component and the diaphragm, the metal film being absent from at least a portion of the opposed region. The metal film and the first electrode are in electrical contact with each other. The first electrode is made of platinum and the metal film is made of a metal material other than platinum.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 29, 2022
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventor: Taiki Tanaka
  • Patent number: RE49167
    Abstract: A Schottky diode is disclosed that includes a silicon carbide substrate, a silicon carbide drift layer, a Schottky contact, and a passivation structure. The silicon carbide drift layer provides an active region and an edge termination region about the active region. The Schottky contact has sides and a top extending between the two sides and includes a Schottky layer over the active region and an anode contact over the Schottky layer. The passivation structure covers the edge termination region, the sides of the Schottky contact, and at least a portion of the top of the Schottky contact. The passivation structure includes a first silicon nitride layer, a silicon dioxide layer over the first silicon nitride layer, and a second silicon nitride layer over the silicon dioxide layer.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 9, 2022
    Assignee: WOLFSPEED, INC.
    Inventors: Van Mieczkowski, Jonathan Young, Qingchun Zhang, John Williams Palmour
  • Patent number: RE49180
    Abstract: A method of forming a three-dimensional object is carried out by: providing a carrier and a pool of immiscible liquid, the pool having a liquid build surface, the carrier and the liquid build surface defining a build region therebetween; filling the build region with a polymerizable liquid, wherein the immiscible liquid is immiscible with the polymerizable liquid (in some embodiments wherein the immiscible liquid has a density greater than the polymerizable liquid); irradiating the build region through at least a portion of the pool of immiscible liquid to form a solid polymer from the polymerizable liquid and advancing the carrier away from the liquid build surface to form the three-dimensional object comprised of the solid polymer from the polymerizable liquid.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: August 23, 2022
    Assignee: Carbon, Inc.
    Inventors: Lloyd M. Robeson, Edward T. Samulski, Alexander Ermoshkin, Joseph M. DeSimone
  • Patent number: RE49205
    Abstract: A rechargeable lithium air battery is provided. The battery contains a ceramic separator forming an anode chamber, a molten lithium anode contained in the anode chamber, an air cathode, and a non-aqueous electrolyte. The cathode has a temperature gradient comprising a low temperature region and a high temperature region, and the temperature gradient provides a flow system for reaction product produced by the battery.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 6, 2022
    Assignee: JOHNSON IP HOLDING, LLC
    Inventors: Lonnie G. Johnson, Tedric D. Campbell
  • Patent number: RE49306
    Abstract: According to one embodiment, there is provided a non-aqueous electrolyte secondary battery including a positive electrode including a positive electrode active material layer, a negative electrode including a negative electrode active material layer, and a non-aqueous electrolyte. At least one of the positive electrode active material layer and the negative electrode active material layer contains carbon dioxide and releases the carbon dioxide in the range of 0.1 ml to 10 ml per 1 g when heated at 350° C. for 1 minute.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: November 22, 2022
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinsuke Matsuno, Hiromichi Kuriyama, Hideki Satake, Takashi Kuboki
  • Patent number: RE49419
    Abstract: An improved structure of nano-scaled and nanostructured Si particles is provided for use as anode material for lithium ion batteries. The Si particles are prepared as a composite coated with MgO and metallurgically bonded over a conductive refractory valve metal support structure.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: February 14, 2023
    Assignee: COMPOSITE MATERIALS TECHNOLOGY, INC.
    Inventors: James Wong, David Frost
  • Patent number: RE49475
    Abstract: A coated cutting tool having a substrate and a surface coating, wherein the coating includes a Ti(C,N) layer of at least one columnar fine-grained MTCVD Ti(C,N) layer with an average grain width of 0.05-0.2 ?m and an atomic ratio of carbon to the sum of carbon and nitrogen (C/(C+N)) contained in the MTCVD Ti(C,N) layer is in average 0.50-0.65.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: March 28, 2023
    Assignee: SANDVIK INTELLECTUAL PROPERTY AB
    Inventor: Carl Bjormander
  • Patent number: RE49677
    Abstract: Techniques for processing materials for manufacture of gallium-containing nitride substrates are disclosed. More specifically, techniques for fabricating and reusing large area substrates using a combination of processing techniques are disclosed. The methods can be applied to fabricating substrates of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, and others. Such substrates can be used for a variety of applications including optoelectronic devices, lasers, light emitting diodes, solar cells, photo electrochemical water splitting and hydrogen generation, photo detectors, integrated circuits, transistors, and others.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: October 3, 2023
    Assignee: SLT Technologies, Inc
    Inventors: Mark P. D'Evelyn, Michael Ragan Krames
  • Patent number: RE49923
    Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and first and second internal electrodes disposed to face each other with respective dielectric layers interposed therebetween; and first and second external electrodes disposed on an external surface of the ceramic body, wherein the dielectric layer contains a barium titanate-based powder particle having a core-shell structure including a core and a shell around the core, the shell having a structure in which titanium is partially substituted with an element having the same oxidation number as that of the titanium in the barium titanate-based powder particle and having an ionic radius different from that of the titanium in the barium titanate-based powder particle, and the shell covers at least 30% of a surface of the core.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Woo Kim, Jong Ho Lee, Min Gi Sin, Hak Kwan Kim, Chin Mo Kim, Chi Hwa Lee, Hong Seok Kim, Woo Sup Kim, Chang Hwa Park
  • Patent number: RE49929
    Abstract: A first embodiment of a substrate for a high-frequency printed wiring board according to the present disclosure is directed to a substrate for a high-frequency printed wiring board, the substrate including: a dielectric layer including a fluororesin and an inorganic filler; and a copper foil layered on at least one surface of the dielectric layer, wherein a surface of the copper foil at the dielectric layer side has a maximum height roughness (Rz) of less than or equal to 2 ?m, and a ratio of the number of inorganic atoms of the inorganic filler to the number of fluorine atoms of the fluororesin in a superficial region of the dielectric layer at the copper foil side is less than or equal to 0.08.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: April 16, 2024
    Assignees: Sumitomo Electric Industries, Ltd., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Shingo Kaimori, Masaaki Yamauchi, Kentaro Okamoto, Satoshi Kiya, Kazuo Murata