Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

Abstract: A display apparatus can include a first subpixel and a second subpixel disposed on a substrate; a first electrode in each of the first subpixel and the second subpixel; a light-emitting layer on the first electrode in each of the first and second subpixels; and a second electrode on the light-emitting layer, in which a structure of the first electrode in the first subpixel is different than a structure of the first electrode in the second subpixel.

Abstract: A display panel and a display apparatus. The display panel includes a first display region and a second display region, an array substrate, a plurality of light-emitting structures, a plurality of pixel driver circuits and at least one isolation structure. The first display region is disposed around at least a portion of the second display region, and the second display region corresponds to a photosensitive device configured to collect light through the second display region. The plurality of light-emitting structures are located on the array substrate and disposed in both the first display region and the second display region. The plurality of pixel driver circuits are disposed in the array substrate, and the plurality of pixel driver circuits are disposed in one-to-one correspondence with the plurality of light-emitting structures.

Abstract: A light emitting diode pixel for a display includes a first subpixel including a first LED sub-unit, a second subpixel including a second LED sub-unit, a third subpixel including a third LED sub-unit, and a bonding layer overlapping the first, second, and third subpixels, in which each of the first, second, and third LED sub-units includes a first type of semiconductor layer and a second type of semiconductor layer, each of the first, second, and third LED sub-units is disposed on a different plane, and light generated from the second subpixel is configured to be emitted to an outside of the light emitting diode pixel by passing through a lesser number of LED sub-units than light generated from the first subpixel and emitted to the outside.

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: A method of patterning a substrate includes forming a multilayer photoresist stack on a substrate. The multilayer photoresist stack includes a first layer of a wet photoresist deposited by spin-on deposition, and a second layer of a dry photoresist deposited by vapor deposition. The first layer is positioned over the second layer. A first relief pattern is formed in the first layer by exposure to a first pattern of actinic radiation of a first wavelength and development of developable portions of the first layer using a first development process. The first relief pattern uncovers portions of the second layer. A multi-color layer of the first relief pattern is formed. The multi-color layer includes the wet photoresist and a third material that is different from the wet photoresist and the dry photoresist. A selective patterning process is executed for uncovered portions of one or two of the wet photoresist, the dry photoresist and the third material.

Abstract: A method for preparing a semiconductor device structure includes forming a nitrogen-containing pattern over a semiconductor substrate. The method also includes performing an energy treating process to form a transformed portion in the semiconductor substrate and covered by the nitrogen-containing pattern. The method further includes etching the semiconductor substrate such that the transformed portion is surrounded by an opening structure.

Abstract: A semiconductor device, including a semiconductor substrate having a diode portion, wherein the diode portion includes: an anode region which is provided on a front surface of the semiconductor substrate and is of a second conductivity type; a trench portion provided so as to extend in a predetermined extending direction on the front surface of the semiconductor substrate; a trench contact portion provided on the front surface of the semiconductor substrate; and a plug region which is provided at a lower end of the trench contact portion and is of a second conductivity type, and which has a doping concentration higher than that of the anode region, wherein a plurality of plug regions, each of which being the plug region, is provided separately from each other along the extending direction, is provided.

Abstract: A display device includes: a substrate including an opening area, a display area, and a non-display area arranged between the opening area and the display area; a first thin-film transistor arranged on the substrate and including a first semiconductor layer including a silicon semiconductor; a first insulating layer covering the first semiconductor layer and defining a lower contact hole overlapping the non-display area, a second thin-film transistor arranged on the first insulating layer and including a second semiconductor layer including an oxide semiconductor; a second insulating layer covering the second semiconductor layer and defining an upper contact hole overlapping the lower contact hole; a display element overlapping the display area, a lower conductive layer overlapping the lower contact hole; and an upper conductive layer arranged on the second insulating layer and connected to the lower conductive layer through the lower contact hole and the upper contact hole.

Abstract: An apparatus includes a first superconductor layer, an insulating layer, and a second superconductor layer, wherein the second superconductor layer is a spin triplet superconductor (STS) layer. In some embodiments, the first superconductor layer is also a STS layer. In some embodiments, the second superconductor layer includes UCoGe. In some embodiments, the insulating layer includes uranium oxide. In some embodiments, the uranium oxide is created by exposing the second superconductor layer to an oxidizing gas, with or without heating. In some embodiments, the first superconductor layer, the insulating layer and the second superconductor layer form a Josephson junction.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

Abstract: An organic electroluminescent device comprises an anode, a first organic light emitting layer, an exciton control layer, a second organic light emitting layer, and a cathode that are successively stacked, wherein the first organic light emitting layer comprises a hole transport type host material and a first doped material; the exciton control layer is provided on the surface of the first organic light emitting layer away from the anode; the exciton control layer comprises a first hole transport material and a first electron transport material; the second organic light emitting layer comprises an electron transport type host material and a second doped material; the cathode is provided on the side of the second organic light emitting layer away from the anode; and one of the first doped material and the second doped material is a fluorescence-doped material, and the other is a phosphorescence-doped material.

Abstract: Structures for a random number generator that include magnetic-tunnel-junction layer stacks and methods of forming such structures. The structure comprises a write line, first and source lines, a first transistor connected by the first source line to a first end of the write line, and a second transistor connected by the second source line to a second end of the write line. The structure further comprises a plurality of magnetic-tunneling-junction layer stacks disposed on the write line between the first and second ends of the write line.

Abstract: The present disclosure relates to a method for forming an integrated chip. The method includes performing a first dicing cut along a first direction and extending into a semiconductor substrate from a first side of the semiconductor substrate. The method includes performing a second dicing cut along the first direction and extending into the semiconductor substrate from a second side of the semiconductor substrate, opposite the first side. The method includes performing a third dicing cut, separate from the second dicing cut, along the first direction and extending into the semiconductor substrate from the second side of the semiconductor substrate.

Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) and first and second electrodes. The MTJ includes: (a) a first ferromagnetic (FM) layer, configured to have a magnetic spin in a first spin direction, and retain the first spin direction while MTJ subjected to electrical current in first and second directions, (b) a second FM layer, configured to have the magnetic spin selectively altered between the first and second spin direction, in response to altering the electrical current between the first and second directions, respectively, and (c) a stack of tunnel barrier (TB) layers, having: a first TB layer disposed over the first FM layer and having a first morphological structure, and a second TB layer, disposed between the first TB layer and the second FM layer and having a second, different, morphological structure. The first and second electrodes are electrically connected to the first and second FM layers, respectively.

Abstract: In an example, a three-dimensional (3D) memory device includes a memory array structure including a first and a second memory array structures, a staircase structure between the first and a second memory array structures in a first lateral direction and including a first and a second staircase zones, and a bridge structure between the first and second staircase zones in a second lateral direction perpendicular to the first lateral direction. Each of the first and second staircase zones includes first and second sub-staircases arranged alternately. Each first sub-staircase includes ascending stairs at different depths. Each second sub-staircase includes descending stairs at different depths. At least one stair in each of the first and second sub-staircases is connected to at least one of the first and second memory array structures through the bridge structure.

Abstract: A method includes depositing a first dielectric layer over a semiconductor substrate, depositing a first electrode layer over the first dielectric layer, etching the first electrode layer to form a first electrode and a second electrode laterally separated from the first electrode, depositing a Spin Orbit Torque (SOT) material on the first electrode and the second electrode, depositing Magnetic Tunnel Junction (MTJ) layers on the SOT material, depositing a second electrode layer on the MTJ layers, etching the SOT material to form a SOT layer extending from the first electrode to the second electrode, etching the MTJ layers to form an MTJ stack on the SOT layer, and etching the second electrode layer to form a top electrode on the MTJ stack.

Abstract: A method of forming a silicon layer includes introducing a source gas containing a precursor material and a carrier gas into a reactor, controlling a gas flow of the source gas through a first main flow controller unit in response to a change of a concentration of the precursor material in the source gas, introducing an auxiliary gas into the reactor, and controlling a gas flow of the auxiliary gas through a second main flow controller unit such that a total gas flow of the source gas and the auxiliary gas into the reactor is held constant when the gas flow of the source gas changes.

Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region buried in the semiconductor substrate providing a body and a second doped region in the semiconductor substrate providing a source. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region that may have void inclusion. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region. A pair of gate contacts are provided at each trench. The pair of gate contacts includes: a first gate contact extending into the first gate lobe at a location laterally offset from the void and a second gate contact extending into the second gate lobe at a location laterally offset from the void.

Abstract: In a method of manufacturing a semiconductor device, a first insulation layer and a first sacrificial layer are alternately and repeatedly formed on a substrate to form a mold layer. A sacrificial layer structure is formed on the mold layer to include an etch stop layer and a second sacrificial layer sequentially stacked. After forming a hard mask on the sacrificial layer structure, the sacrificial layer structure and the mold layer are etched by a dry etching process using the hard mask as an etching mask to form a channel hole exposing an upper surface of the substrate and form a recess on a sidewall of the second sacrificial layer adjacent to the channel hole. A memory channel structure is formed in the channel hole. The first sacrificial layer is replaced with a gate electrode.