Patents Examined by Shahed Ahmed
  • Patent number: 10734521
    Abstract: The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: August 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mirco Cantoro, Yeoncheol Heo
  • Patent number: 10734516
    Abstract: Embodiments of field effect transistor (FET) circuits, RF switches, and devices include source and drain terminals coupled to an active surface of a semiconductor substrate, a channel in the substrate between the source and drain terminals, and a plurality of gate structures coupled to the active surface over the channel. A channel contact is coupled to the active surface over the channel between a first pair of the gate structures, and a first capacitor is electrically coupled between the channel contact and a gate structure of the plurality of gate structures.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 4, 2020
    Assignee: NXP USA, Inc.
    Inventor: Venkata Naga Koushik Malladi
  • Patent number: 10734391
    Abstract: A first contact hole is formed so as to extend to a NiSi layer as a lower wiring conductor layer connecting to an N+ layer of an SGT formed within a Si pillar, and so as to extend through a NiSi layer as an upper wiring conductor layer connecting to a gate TiN layer, and a NiSi layer as an intermediate wiring conductor layer connecting to an N+ layer. A second contact hole is formed so as to extend to the NiSi layer, and surround, in plan view, the first contact hole. An insulating SiO2 layer is formed on a side surface of the NiSi layer. A wiring metal layer in the contact holes connects the NiSi layer and the NiSi layer to each other.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: August 4, 2020
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 10734557
    Abstract: A light-emitting device includes a package structure and a light-emitting chip. The package structure has a light exiting surface, a rear surface facing away from the light exiting surface, a groove inward recessed on the rear surface, and an outer surrounding side wall surrounding the groove. The light-emitting chip is disposed in the groove. The width of the package structure gradually decreases from the light exiting surface to the rear surface. The width of the groove gradually increases from inside to outside of the groove.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: August 4, 2020
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Liangliang Luo, Shu-yong Jia, Wen Lee, Ke-qin Guo
  • Patent number: 10734384
    Abstract: Vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits are disclosed. A horizontal footprint of a CFET cell circuit may be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type channel structures. The N-type and P-type channel structures may be formed of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Bin Yang, Gengming Tao
  • Patent number: 10734408
    Abstract: A non-volatile memory system is provided that includes a plurality of NAND strings of non-volatile storage elements, each non-volatile storage element including a control gate, a tunneling layer, a floating gate, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the floating gate, and the floating gate is disposed between the tunneling layer and the blocking layer.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 4, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Yingda Dong, Yangyin Chen, Yukihiro Sakotsubo
  • Patent number: 10727213
    Abstract: Gates of semiconductor switching elements are connected to a gate control wiring pattern. The gate control wiring pattern is further connected to a gate control terminal and a filter terminal which are connected by an element for forming a filter outside a housing. The filter terminal and the gate control terminal are connected to the gate control wiring pattern in such a manner that a section electrically connecting the filter terminal and the gate control terminal overlaps with at least a part of a section electrically connecting the gates of the semiconductor switching elements on the gate control wiring pattern.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 28, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junichi Nakashima, Yoshiko Tamada, Yasushi Nakayama
  • Patent number: 10725205
    Abstract: A forensic weather analyzer compares actual meteorological readings with data from multiple weather models. The data is compared and a forensic weather model is selected as the weather model that most closely matches the meteorological readings. The forensic weather model is then used to provide meteorological information pertaining to a weather event such as a hurricane, at a specific location such as a street address.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: July 28, 2020
    Assignee: FORENSIC WEATHER CONSULTANTS, LLC
    Inventor: Howard Gregory Altschule
  • Patent number: 10727230
    Abstract: An integrated semiconductor device includes a first semiconductor device, an ILD layer and a second semiconductor device. The first semiconductor device has a first transistor structure. The ILD layer is over the first semiconductor device and has a thickness in a range substantially from 10 nm to 100 nm. The second semiconductor device is over the ILD layer and has a 2D material layer as a channel layer of a second transistor structure thereof.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Chun-Chieh Lu, Meng-Hsuan Hsiao, Ling-Yen Yeh, Carlos H. Diaz, Tung-Ying Lee
  • Patent number: 10720421
    Abstract: In a circuit portion, a p+-type diffusion region penetrates, in the depth direction, an n?-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p++-type contact region, an n+-type diffusion region, and a p+-type diffusion region are selectively provided in a p+-type diffusion region on the front side of the base substrate. The p+-type diffusion region penetrates the p?-type diffusion region in the depth direction, on the outer periphery of the p?-type diffusion region. An n+-type source region, the p+-type diffusion region, the p++-type contact region, and the n+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: July 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiaki Toyoda, Hideaki Katakura
  • Patent number: 10714619
    Abstract: A method for fabricating a semiconductor device includes forming a doped semiconductor layer on a substrate and forming a fin structure disposed on the doped semiconductor layer. The fin structure is doped with a p-type dopant. The method further includes forming a source/drain region within an upper portion of the fin structure and forming a fin sidewall along a lower portion of the fin structure. The fin sidewall has the p-type dopant.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Wei-Yang Lee, Chia-Chun Lan, Chia-Ling Chan, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10704167
    Abstract: The method for drawing a fiber with a textured surface comprises the following steps: —forming of a preform from which the fiber is to be drawn with a textured surface; —addition of an outer layer to the textured preform to preserve the shape of the texture of the preform surface during the drawing operation; —drawing of a fiber from the preform, whereby the fiber keeps the formed texture of the preform surface and —removing the additional outer layer to leave the original surface textured fiber exposed. The obtained fiber can be used as a mold to form a textured hollow channel in another material, as a surface coating and as a pressure detector.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: July 7, 2020
    Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
    Inventors: Fabien Sorin, Tung Dang Nguyen, Yunpeng Qu, Alexis Page, Wei Yan
  • Patent number: 10707295
    Abstract: A semiconductor device includes a semiconductor substrate, a capacitor structure, a first contact plug, and a spacer. The capacitor structure is over the semiconductor substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric, and a top electrode. The bottom electrode is over the semiconductor substrate. The capacitor dielectric is over a first portion of the bottom electrode. The top electrode is over the capacitor dielectric. The first contact plug is on and connected to a second portion of the bottom electrode. The spacer is on at least a sidewall of the second portion of the bottom electrode.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: An-Hao Cheng
  • Patent number: 10700091
    Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David Ross Economy, John Mark Meldrim, Haoyu Li, Yongjun Jeff Hu, Christopher W. Petz, Daniel Billingsley, Everett A. McTeer
  • Patent number: 10700022
    Abstract: The present disclosure discloses an inductor structure mounted on a PCB board and a voltage regulator module having the same. The inductor structure includes an inductor core and an inductor winding. The PCB board is provided with at least one hollow part, and the inductor structure further comprises a plurality of copper strips used as the inductor windings of the inductor structure. The copper strips are spaced apart in the hollow part so as to form a plurality of through holes, and the leg of the inductor core is correspondingly inserted into the through hole at the corresponding position of the hollow part.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: June 30, 2020
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Xiangxing Zheng, Wenhua Li, Quansong Luo, Yuanyuan Dan, Haijun Yang, Shaohua Zhu
  • Patent number: 10693093
    Abstract: Provided is a light-emitting element with high external quantum efficiency and a low drive voltage. The light-emitting element includes a light-emitting layer which contains a phosphorescent compound and a material exhibiting thermally activated delayed fluorescence between a pair of electrodes, wherein a peak of a fluorescence spectrum and/or a peak of a phosphorescence spectrum of the material exhibiting thermally activated delayed fluorescence overlap(s) with a lowest-energy-side absorption band in an absorption spectrum of the phosphorescent compound, and wherein the phosphorescent compound exhibits phosphorescence in the light-emitting layer by voltage application between the pair of electrodes.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: June 23, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Satoshi Seo
  • Patent number: 10686051
    Abstract: A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 16, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jeong Hwan Park, Seung Sik Park, Ha Yong Yang
  • Patent number: 10686152
    Abstract: Emission efficiency of a light-emitting element is improved. The light-emitting element has a pair of electrodes and an EL layer between the pair of electrodes. The EL layer includes a first light-emitting layer and a second light-emitting layer. The first light-emitting layer includes a fluorescent material and a host material. The second light-emitting layer includes a phosphorescent material, a first organic compound, and a second organic compound. An emission spectrum of the second light-emitting layer has a peak in a yellow wavelength region. The first organic compound and the second organic compound form an exciplex.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Takahiro Ishisone, Nobuharu Ohsawa, Yusuke Nonaka, Toshiki Sasaki
  • Patent number: 10686059
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Yu-Cheng Liu, Wei-Ting Chen
  • Patent number: 10684545
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a assist layer over the material layer. The assist layer includes a polymer backbone, an acid labile group (ALG) bonded to the polymer backbone, and a floating group bonded to the polymer backbone. The floating group includes carbon fluoride (CxFy). The method also includes forming a resist layer over the assist layer and patterning the resist layer.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Ching-Yu Chang, Chin-Hsiang Lin