Patents Examined by Shahed Ahmed
  • Patent number: 11522119
    Abstract: A piezoelectric actuator includes a first electrode, a first piezoelectric body disposed at one side of the first electrode in a thickness direction of the first electrode, an individual electrode disposed at one side of the first piezoelectric body in the thickness direction, a second piezoelectric body disposed at one side of the individual electrode in the thickness direction, a second electrode disposed at one side of the second piezoelectric body in the thickness direction, a wiring that electrically connects to the individual electrode, a first contact, and a second contact. At the first and the second contacts, the first electrode and the second electrode electrically connect to each other. The first contact is disposed at one side of the individual electrode in a perpendicular direction perpendicular to the thickness direction. The second contact is disposed at the other side of the individual electrode in the perpendicular direction.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: December 6, 2022
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Rui Wang
  • Patent number: 11521898
    Abstract: A memory device is provided. The memory device includes a substrate, a stacked structure, and a contact. The substrate includes a memory array region and a staircase region. The stacked structure is located on the substrate in the memory array region and the staircase region. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers alternately stacked on each other. Each of the plurality of conductive layers includes a main body and an end part. The main body is located in the memory array region and extends to the staircase region. The end part is connected to the main body and is located in the staircase region. A thickness of the end part is greater than a thickness of the main body. The contact lands on and is connected to the end part.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: December 6, 2022
    Assignee: MACRONIX INIERNATIONAL CO., LTD.
    Inventor: Min-Feng Hung
  • Patent number: 11522116
    Abstract: A vertical Josephson junction device includes a substrate, and an epitaxial stack formed on the substrate. The vertical Josephson junction device includes a first superconducting electrode embedded in the epitaxial stack, and a second superconducting electrode embedded in the epitaxial stack, the second superconducting electrode being separated from the first superconducting electrode by a dielectric layer. In operation, the first superconducting electrode, the dielectric layer, and the second superconducting electrode form a vertical Josephson junction.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: December 6, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Holmes, Devendra K. Sadana
  • Patent number: 11521978
    Abstract: The present application discloses a semiconductor device with a programmable unit and a method for fabricating the semiconductor device. The semiconductor device includes a substrate comprising a first region and a second region; a first semiconductor element positioned in the first region of the substrate; a second semiconductor element positioned in the first region of the substrate and electrically coupled to the first semiconductor element; and a programmable unit positioned in the second region and electrically connected to the first semiconductor element.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: December 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Cheng-Ling Yang
  • Patent number: 11522075
    Abstract: A semiconductor device according to one or more embodiments may include a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type with a higher impurity concentration than an impurity concentration of the first semiconductor region, the second semiconductor region being provided on a first principal surface of the first semiconductor region, a third semiconductor region of a second conductivity type provided on an upper surface of the second semiconductor region, the third semiconductor region being doped with an impurity in accordance with an impurity concentration profile including peaks along a film thickness direction, a fourth semiconductor region of the first conductivity type provided on an upper surface of the third semiconductor region.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: December 6, 2022
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventor: Yuuichi Oshino
  • Patent number: 11522053
    Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: December 6, 2022
    Assignees: Amplexia, LLC, X-FAB Global Services GmbH
    Inventors: Brendan Toner, Zhengchao Liu, Gary M. Dolny, William R. Richards, Manoj Chandrika Reghunathan, Stefan Eisenbrandt, Christoph Ellmers
  • Patent number: 11515144
    Abstract: Methods for filling the gap of a semiconductor feature comprising exposure of a substrate surface to a precursor and reactant and an anneal environment to decrease the wet etch rate ratio of the deposited film and fill the gap.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: November 29, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Keiichi Tanaka, Andrew Short, Mandyam Sriram, Srinivas Gandikota
  • Patent number: 11515433
    Abstract: A flexible wire comprises a conductive core surrounded by one or more radial p-n diodes and alternating conductive and non-conductive bands along an outermost surface. Methods for producing the wire are also disclosed, as are textiles and other flexible materials comprising or consisting of such flexible wires.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: November 29, 2022
    Assignee: University of Louisville Research Foundation, Inc.
    Inventor: Cindy Harnett
  • Patent number: 11506799
    Abstract: A radiation detector has a photoelectric conversion element array having a light receiving unit and a plurality of bonding pads; a scintillator layer stacked on the photoelectric conversion element array; a resin frame formed on the photoelectric conversion element array so as to pass between the scintillator layer and the bonding pads away from the scintillator layer and the bonding pads and so as to surround the scintillator layer; and a protection film covering the scintillator layer and having an outer edge located on the resin frame; a first distance between an inner edge of the resin frame and an outer edge of the scintillator layer is shorter than a second distance between an outer edge of the resin frame and an outer edge of the photoelectric conversion element array; the outer edge and a groove are processed with a laser beam.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: November 22, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventor: Syouji Kurebayashi
  • Patent number: 11508809
    Abstract: The present disclosure discloses a semiconductor device and a preparation method thereof. The semiconductor device includes: an N+ substrate, a plurality of openings opening toward a back surface formed in the N+ substrate; an N? epitaxial layer formed on the N+ substrate, the N? epitaxial layer including: an active area epitaxial layer including a plurality of P++ area rings and a plurality of groove structures, wherein single groove structure is formed on single P++ area ring; a terminal area epitaxial layer including an N+ field stop ring and a plurality of P+ guard rings; a Schottky contact formed on the active area epitaxial layer, a passivation layer formed on the terminal area epitaxial layer, and ohmic contacts formed on the back surface of the N+ substrate and in the plurality of openings.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: November 22, 2022
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yidan Tang, Xinyu Liu, Yun Bai, Shengxu Dong, Chengyue Yang
  • Patent number: 11508840
    Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a second well region formed in a terminal portion sometimes reduces a breakdown voltage. In a SiC-MOSFET including Schottky diodes according to the present invention, the second well region formed in the terminal portion has a non-ohmic connection to a source electrode, and a field limiting layer lower in impurity concentration than the second well region is formed in a surface layer area of the second well region which is a region facing a gate electrode through a gate insulating film.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 22, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shiro Hino, Yuichi Nagahisa, Koji Sadamatsu, Hideyuki Hatta, Kotaro Kawahara
  • Patent number: 11508814
    Abstract: A transistor including at least one two-dimensional (2D) channel is disclosed. A transistor according to some example embodiments includes first to third electrodes separated from each other, and a channel layer that is in contact with the first and second electrodes, parallel to the third electrode, and includes at least one 2D channel. The at least one 2D channel includes at least two regions having different doping concentrations. A transistor according to some example embodiments includes: first to third electrodes separated from each other; a 2D channel layer that is in contact with the first and second electrodes and parallel to the third electrode; a first doping layer disposed under the 2D channel layer corresponding to the first electrode; and a second doping layer disposed under the 2D channel layer corresponding to the second electrode, wherein the first and second doping layers contact the 2D channel layer.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minhyun Lee, Minsu Seol, Hyeonjin Shin
  • Patent number: 11508817
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Patent number: 11502205
    Abstract: A semiconductor device according to an embodiment includes first and second electrode, and semiconductor layer between the first and the second electrode. The semiconductor layer has first and second plane. The semiconductor layer includes first region of first conductivity type, second region of second conductivity type between the first plane and the first region, third region of second conductivity type between the first plane and the first region and, fourth region of second conductivity type between the second and the third region, and fifth region of first conductivity type having first portion provided between the first and the fourth region. Width of the fourth region is larger than that of the second region. Distance between the second region and the first portion is smaller than distance between the second and the fourth region. And width of the first portion is smaller than that of the fourth region.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 15, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yoichi Hori, Masakazu Kobayashi
  • Patent number: 11502140
    Abstract: A display apparatus including an organic light-emitting display panel and a touch sensing unit disposed on the organic light-emitting display panel is disclosed. The touch sensing unit includes a touch electrode and a wiring part connected to the touch electrode. The wiring part of the touch sensing unit passes a protruding member disposed on a non-display region of the organic light-emitting display panel, and forms a first wiring part which does not overlap the protruding member, a second wiring part overlapping the protruding part, and a connection wiring part disposed between the first and second wiring parts and having a wiring width less than the first and second wiring parts so as to overlap an edge of the protruding member.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: November 15, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chiwook An, Miyoung Kim, Jongseok Kim, Kiho Bang
  • Patent number: 11502230
    Abstract: A light emitting device including first, second, and third light emitting parts disposed one over another and each including a first-type semiconductor layer, an active layer, and a second-type semiconductor layer, a first conductive pattern at least partially disposed between the second and third light emitting parts, the first conductive pattern including a first portion electrically coupled with at least one of the first-type and second-type semiconductor layers of the first and second light emitting parts, and a second portion extending from the first portion and disposed on one surface of the second light emitting part between the second and third light emitting parts, and a second conductive pattern disposed on the third light emitting part and electrically coupled with the first conductive pattern, in which the second conductive pattern at least partially overlaps with the second portion of the first conductive pattern.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 15, 2022
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Seong Gyu Jang, Chan Seob Shin, Seom Geun Lee, Ho Joon Lee, Jong Hyeon Chae
  • Patent number: 11495460
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate, and forming a first layer over the material layer. The method also includes forming a second layer over the first layer, and the second layer includes an auxiliary. The method further includes forming a third layer over the second layer, and the third layer includes an inorganic material, the inorganic material includes a plurality of metallic cores, and a plurality of first linkers bonded to the metallic cores. A topmost surface of the second layer is in direct contact with a bottommost surface of the third layer. The method includes exposing a portion of the second layer by performing an exposure process, and the auxiliary reacts with the first linkers during the exposure process.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Chin-Hsiang Lin, Ching-Yu Chang
  • Patent number: 11495543
    Abstract: A semiconductor device includes a substrate and a first semiconductor layer and a second semiconductor layer each extending in a first direction perpendicular to a surface of the substrate. Furthermore, the semiconductor device includes a first plug provided on the first semiconductor layer and a second plug provided on the second semiconductor layers, and a connection wiring having an upper surface that is at a same height along the first direction as upper surfaces of the first and second plugs, and having a lower surface that is at a same height along the first direction as lower surfaces of the first and second plugs. Furthermore, the semiconductor device includes a first wiring provided on the first plug and the connection wiring and a second wiring provided on the second plug and the connection wiring.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: November 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Tetsuaki Utsumi
  • Patent number: 11495659
    Abstract: A semiconductor device includes a semiconductor substrate, a capacitor structure, a first contact plug, and a spacer. The capacitor structure is over the semiconductor substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric, and a top electrode. The bottom electrode is over the semiconductor substrate. The capacitor dielectric is over a first portion of the bottom electrode. The top electrode is over the capacitor dielectric. The first contact plug is over and electrically connected to a second portion of the bottom electrode. The spacer is adjacent at least a sidewall of the second portion of the bottom electrode.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: An-Hao Cheng
  • Patent number: 11490811
    Abstract: An embodiment of a sensor device includes a base substrate, a circuit pattern formed overlying the interior surface of the substrate, a physiological characteristic sensor element on the exterior surface of the substrate, conductive plug elements located in vias formed through the substrate, each conductive plug element having one end coupled to a sensor electrode, and having another end coupled to the circuit pattern, a multilayer component stack carried on the substrate and connected to the circuit pattern, the stack including features and components to provide processing and wireless communication functionality for sensor data obtained in association with operation of the sensor device, and an enclosure structure coupled to the substrate to enclose the interior surface of the substrate, the circuit pattern, and the stack.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 8, 2022
    Assignee: Medtronic MiniMed, Inc.
    Inventors: Daniel Hahn, David L. Probst, Randal C. Schulhauser, Mohsen Askarinya, Patrick W. Kinzie, Thomas P. Miltich, Mark D. Breyen, Santhisagar Vaddiraju