Abstract: In an embodiment a method for singulating components from a component composite includes providing the component composite comprising a structured substrate including component carrier bodies and connecting portions arranged between the component carrier bodies, and a base material, in which the connecting portions of the structured substrate are at least partially embedded, removing the base material in separating regions of the component composite, which include the connecting portions and singulating the component composite at the separating regions to form the components.

Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

Abstract: The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion.

Abstract: The present invention provides a field effect transistor device and a method for improving the short-channel effect and the output characteristics using the same. The field effect transistor device comprises an active layer comprising a source region, a drain region, and a channel region located between the source region and the drain region; when the device is turned on, an effective channel and an equivalent source and/or equivalent drain away from the effective channel are formed in the channel region, and the field effect transistor device connects the source region with the drain region through the effective channel, and the equivalent source and/or equivalent drain to form an operating current.

Abstract: Provided are display device and method of fabricating the same. The display device comprises a substrate, a first semiconductor layer, a first gate insulating layer, a first gate electrode dispose, a first interlayer insulating layer, a first oxide semiconductor layer, a second gate insulating layer and a second gate electrode sequentially disposed on the substrate, spacers disposed on side surfaces of the second gate electrode, and a second interlayer insulating layer disposed on the spacers, wherein each of the spacers comprises a first spacer disposed to contact a side surface of the second gate electrode and a second spacer disposed on the first spacer. A concentration of hydrogen included in the first spacer is lower than a concentration of hydrogen included in the second spacer.

Abstract: A display device includes a substrate that includes a display area and a transmissive area, a first blocking layer that is disposed on the display area of the substrate, and disposed on a first surface of the substrate, a second blocking layer that is disposed in the display area of the substrate, and disposed on a second surface of the substrate opposite to the first surface, an insulation layer that is disposed on the first blocking layer, a transistor that is disposed on the insulation layer, and a light emitting element that is connected to the transistor.

Abstract: A semiconductor device includes: an N? drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N? drift layer; and an N buffer layer of the first conductivity type formed under the N? drift layer and higher in peak impurity concentration than the N? drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N? drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.

Abstract: The present disclosure discloses a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate, a doped epitaxial layer located on one side of the substrate, a channel layer located on one side of the doped epitaxial layer away from the substrate, a potential barrier layer located on one side of the channel layer away from the doped epitaxial layer, and a first electrode and a second electrode located on one side of the potential barrier layer away from the channel layer, wherein the first electrode penetrates the potential barrier layer, the channel layer and part of the doped epitaxial layer, the first electrode forms a Schottky contact with the channel layer, and a resistance of the part of the doped epitaxial layer in contact with the first electrode is greater than a resistance of the channel layer.

Abstract: A semiconductor device includes a first structure and a second structure thereon. The first structure includes a substrate, circuit elements on the substrate, a lower interconnection structure electrically connected to the circuit elements, and lower bonding pads, which are electrically connected to the lower interconnection structure. The second structure includes a stack structure including: gate electrodes and interlayer insulating layers, which are alternately stacked and spaced apart in a vertical direction; a plate layer that extends on the stack structure; channel structures within the stack structure, separation regions, which penetrate at least partially through the stack structure, and upper bonding pads, which are electrically connected to the gate electrodes and the channel structures, and are bonded to corresponding ones of the lower bonding pads.

Abstract: A light-emitting element includes: a cathode; an anode; and an electron-transport layer, a light-emitting layer, and a hole-transport layer provided, between the cathode and the anode, in a stated order from the cathode. At least one of the electron-transport layer or the hole-transport layer includes: a first charge-transport layer and a second charge-transport layer containing different carrier-transport materials. The light-emitting element includes, in plan view, a first region including the first charge-transport layer, and a second region including the second charge-transport layer. The light-emitting element shares the anode and the cathode between the first region and the second region.

Abstract: A superconducting quantum interference apparatus comprising a planar array of loops where each loop constitutes a superconducting quantum interference device, and a magnetic shield disposed over part of one of the loops so to protect the covered part of the loop from exposure to a magnetic field.

Abstract: A semiconductor device comprises: a substrate including first and second buried source/drain layers; a first nano sheet stack including first nano sheets stacked in a direction vertical to the substrate; a second nano sheet stack including second nano sheets stacked in a direction vertical to the substrate; an isolation wall disposed between the first nano sheet stack and the second nano sheet stack; first gate covering portions of the first nano sheet stack and extending in a direction vertical to the substrate; second gate covering portions of the second nano sheet stack and extending in a direction vertical to the substrate; first common source/drain layers connected to end portions of the first nano sheets and to the first buried source/drain layers; and second common source/drain layers connected to end portions of the second nano sheets and to the second buried source/drain layers.

Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

Abstract: A display apparatus can include a first subpixel and a second subpixel disposed on a substrate; a first electrode in each of the first subpixel and the second subpixel; a light-emitting layer on the first electrode in each of the first and second subpixels; and a second electrode on the light-emitting layer, in which a structure of the first electrode in the first subpixel is different than a structure of the first electrode in the second subpixel.

Abstract: A light emitting diode pixel for a display includes a first subpixel including a first LED sub-unit, a second subpixel including a second LED sub-unit, a third subpixel including a third LED sub-unit, and a bonding layer overlapping the first, second, and third subpixels, in which each of the first, second, and third LED sub-units includes a first type of semiconductor layer and a second type of semiconductor layer, each of the first, second, and third LED sub-units is disposed on a different plane, and light generated from the second subpixel is configured to be emitted to an outside of the light emitting diode pixel by passing through a lesser number of LED sub-units than light generated from the first subpixel and emitted to the outside.

Abstract: A display panel and a display apparatus. The display panel includes a first display region and a second display region, an array substrate, a plurality of light-emitting structures, a plurality of pixel driver circuits and at least one isolation structure. The first display region is disposed around at least a portion of the second display region, and the second display region corresponds to a photosensitive device configured to collect light through the second display region. The plurality of light-emitting structures are located on the array substrate and disposed in both the first display region and the second display region. The plurality of pixel driver circuits are disposed in the array substrate, and the plurality of pixel driver circuits are disposed in one-to-one correspondence with the plurality of light-emitting structures.

Abstract: A method of patterning a substrate includes forming a multilayer photoresist stack on a substrate. The multilayer photoresist stack includes a first layer of a wet photoresist deposited by spin-on deposition, and a second layer of a dry photoresist deposited by vapor deposition. The first layer is positioned over the second layer. A first relief pattern is formed in the first layer by exposure to a first pattern of actinic radiation of a first wavelength and development of developable portions of the first layer using a first development process. The first relief pattern uncovers portions of the second layer. A multi-color layer of the first relief pattern is formed. The multi-color layer includes the wet photoresist and a third material that is different from the wet photoresist and the dry photoresist. A selective patterning process is executed for uncovered portions of one or two of the wet photoresist, the dry photoresist and the third material.

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

Abstract: A semiconductor device, including a semiconductor substrate having a diode portion, wherein the diode portion includes: an anode region which is provided on a front surface of the semiconductor substrate and is of a second conductivity type; a trench portion provided so as to extend in a predetermined extending direction on the front surface of the semiconductor substrate; a trench contact portion provided on the front surface of the semiconductor substrate; and a plug region which is provided at a lower end of the trench contact portion and is of a second conductivity type, and which has a doping concentration higher than that of the anode region, wherein a plurality of plug regions, each of which being the plug region, is provided separately from each other along the extending direction, is provided.

Abstract: An apparatus includes a first superconductor layer, an insulating layer, and a second superconductor layer, wherein the second superconductor layer is a spin triplet superconductor (STS) layer. In some embodiments, the first superconductor layer is also a STS layer. In some embodiments, the second superconductor layer includes UCoGe. In some embodiments, the insulating layer includes uranium oxide. In some embodiments, the uranium oxide is created by exposing the second superconductor layer to an oxidizing gas, with or without heating. In some embodiments, the first superconductor layer, the insulating layer and the second superconductor layer form a Josephson junction.