Abstract: A display apparatus including an organic light-emitting display panel and a touch sensing unit disposed on the organic light-emitting display panel is disclosed. The touch sensing unit includes a touch electrode and a wiring part connected to the touch electrode. The wiring part of the touch sensing unit passes a protruding member disposed on a non-display region of the organic light-emitting display panel, and forms a first wiring part which does not overlap the protruding member, a second wiring part overlapping the protruding part, and a connection wiring part disposed between the first and second wiring parts and having a wiring width less than the first and second wiring parts so as to overlap an edge of the protruding member.

Abstract: A semiconductor memory device includes a semiconductor substrate including an upper surface extending in a horizontal direction, a source structure including a trench extending in the horizontal direction, the source structure disposed above the semiconductor substrate, a metal structure in the trench of the source structure and connecting the source structure to the semiconductor substrate, and memory cell strings disposed on both sides of the trench and connected to the source structure.

Abstract: The present application discloses a method for manufacturing fin field effect transistors, comprising: step 1: performing first time etching to form top portions of fins, each of the top portions is divided into a first section and a second section; step 2: forming sacrificial sidewalls on the side surfaces of the second section but not on the side surfaces of the first section; step 3: forming a doped dielectric layer to coat the side surfaces of the first section; step 4: performing a dopant drive process to diffuse dopants of the doped dielectric layer into the first section; step 5: removing the doped dielectric layer and the sacrificial sidewalls; step 6: performing second time etching to form bottom portions of the fins; and step 7: forming a dielectric isolation layer between adjacent fins.

Abstract: A display device includes: ferritin encaging a first quantum dot and modified with a first peptide bound to a first pixel electrode; and ferritin encaging a second quantum dot and modified with a second peptide bound to a second pixel electrode. A first metal material and a second metal material are of different types.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked layer body including conductive layers stacked to be apart from each other in a first direction, and including a stair-like end with rising parts and terrace parts, wherein successive first conductive layers including an uppermost conductive layer function as select gate lines for a NAND string, and a first contact connected to the uppermost conductive layer provided to correspond to a first rising part which is an uppermost one of the rising parts. The first contact passes through the uppermost conductive layer to be further connected to a first conductive layer adjacent to the uppermost conductive layer.

Abstract: A semiconductor device includes a first electrode, a second electrode, a semiconductor part located between the first electrode and the second electrode, a third electrode located in the semiconductor part, an insulating film located between the third electrode and the semiconductor part, an insulating member located in the semiconductor part at a position separated from the insulating film, a fourth electrode located in the insulating member, and a compressive stress member located in the fourth electrode. The compressive stress member has compressive stress along a first direction. The first direction is from the first electrode toward the second electrode.

Abstract: A photodetector, a preparation method for a photodetector, a photodetector array and a photodetection terminal. The photodetector comprises a substrate (11) and an optical resonant cavity (10) formed on the substrate (11).

Abstract: A semiconductor device includes a stacked body including a conductive pattern and an insulating pattern, a cell plug passing through the stacked body, a semiconductor layer, a peripheral transistor arranged on the semiconductor layer, a first conductor coupling the peripheral transistor to the cell plug, a second conductor coupled to the conductive pattern, a pass plug coupled to the second conductor, and a pass gate surrounding the pass plug, wherein the pass gate is arranged at substantially a same level as the semiconductor layer.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: An electronic neuron device that includes a thresholding unit which utilizes current-induced spin-orbit torque (SOT). A two-step switching scheme is implemented with the device. In the first step, a charge current through heavy metal (HM) places the magnetization of a nano-magnet along the hard-axis (i.e. an unstable point for the magnet). In the second step, the device receives a current (from an electronic synapse) which moves the magnetization from the unstable point to one of the two stable states. The polarity of the net synaptic current determines the final orientation of the magnetization. A resistive crossbar array may also be provided which functions as the synapse generating a bipolar current that is a weighted sum of the inputs of the device.

Abstract: A cell region of a semiconductor device includes a first and second isolation dummy gates extending along a first direction. The semiconductor device further includes a first gate extending along the first direction and between the first isolation dummy gate and the second isolation dummy gate. The semiconductor device includes a second gate extending along the first direction, the second gate being between the first isolation dummy gate and the second isolation dummy gate relative to a second direction perpendicular to the first direction. The semiconductor device also includes a first active region and a second active region. The first active region extending in the second direction between the first isolation dummy gate and the second isolation dummy gate. The first active region has a first length in the second direction, and the second active region has a second length in the second direction different from the first length.

Abstract: Selective self-assembled monolayer patterning with sacrificial layer for devices is provided herein. A sensor device can include a handle layer and a device layer that comprises a first side and a second side. First portions of the first side are operatively connected to defined portions of the handle layer. At least one area of the second side comprises an anti-stiction area formed with an anti-stiction coating. The device can also include a Complementary Metal-Oxide-Semiconductor (CMOS) wafer operatively connected to second portions of the second side of the device layer. The CMOS wafer comprises at least one bump stop. The anti-stiction area faces the at least one bump stop.

Abstract: A monolithically integrated bidirectional switch includes: an output terminal; a control terminal; a compound semiconductor substrate; a common drift region in the compound semiconductor substrate and in series between the input terminal and the output terminal; a first gate; and a second gate. The first gate is electrically connected to the control terminal and the second gate is electrically connected to the input terminal, or one of the first gate and the second gate is a normally-on gate and the other one of the first gate and the second gate is a normally-off gate. In either case, the monolithically integrated bidirectional switch is configured to conduct current in a single direction from the input terminal to the output terminal through the common drift region. A corresponding power electronic system that uses the monolithically integrated bidirectional switch is also described.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer, a first floating gate electrode, a first control gate electrode, an erase gate electrode, and a blocking layer. The semiconductor substrate has a first source/drain region. The first semiconductor layer extends upward from the first source/drain region of the semiconductor substrate. The first floating gate electrode surrounds the first semiconductor layer. The first control gate electrode surrounds the first floating gate electrode and the first semiconductor layer. The erase gate electrode is over the first floating gate electrode and the first control gate electrode. The erase gate electrode surrounds the first semiconductor layer. The blocking layer has a first portion between the first floating gate electrode and the first control gate electrode and a second portion between the erase gate electrode and the first semiconductor layer.

Abstract: Coupled polysilicon guard rings for enhancing breakdown voltage in a power semiconductor device are presented herein. Polysilicon guard rings are disposed above the power device drift region and electrically coupled to power device regions (e.g., device diffusions) so as to spread electric fields associated with an operating voltage. Additionally, PN junctions (i.e., p-type and n-type junctions) are formed within the polysilicon guard rings to operate in reverse bias with a low leakage current between the power device regions (e.g., device diffusions). Low leakage current may advantageously enhance the electric field spreading without deleteriously affecting existing (i.e., normal) power device performance; and enhanced electric field spreading may in turn reduce breakdown-voltage drift.

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.

Abstract: Schottky diode and method for fabricating the same disclosed. The Schottky diode includes a gallium oxide layer that is a semiconductor layer doped with a first-type dopant, a cathode in ohmic contact with the gallium oxide layer and an anode having a Schottky contact metal layer in Schottky contact with the gallium oxide layer. The gallium oxide layer is in contact with an interface with the Schottky contact metal layer, contains a second-type dopant of a conductivity opposite to that of the first-type dopant, and has an interlayer which is a region where a concentration of the second-type dopant decreases as it moves away from an interface with the Schottky contact metal layer.

Abstract: A micro-electromechanical system (MEMS) device includes a movable comb structure located in a cavity within an enclosure, and a stationary structure affixed to the enclosure. The movable comb structure includes a comb shaft portion and movable comb fingers laterally protruding from the comb shaft portion. The movable comb structure includes a metallic material portion. The movable structure and the stationary structure are configured to generate an electrical output signal based on lateral movement of the movable structure relative to the stationary structure.

Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. Etches are performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.