Abstract: An organic light-emitting diode (OLED) deposition system has a workpiece transport system configured to position a workpiece within the OLED deposition system under vacuum conditions, a deposition chamber configured to deposit a first layer of organic material onto the workpiece, a metrology system having one or more sensors measure of the workpiece after deposition in the deposition chamber, and a control system to control a deposition of the layer of organic material onto the workpiece. The metrology system includes a digital holographic microscope positioned to receive light from the workpiece and generate a thickness profile measurement of a layer on the workpiece. The control system is configured to adjust processing of a subsequent workpiece at the deposition chamber or adjust processing of the workpiece at a subsequent deposition chamber based on the thickness profile.

Abstract: A three-dimensional semiconductor device includes a first substrate; a plurality of first transistors on the first substrate; a second substrate on the plurality of first transistors; a plurality of second transistors on the second substrate; and an interconnection portion electrically connecting the plurality of first transistors and the plurality of second transistors. Each of the plurality of first transistors includes a first gate insulating film on the first substrate and having a first hydrogen content. Each of the plurality of second transistors includes a second gate insulating film on the second substrate and having a second hydrogen content. The second hydrogen content is greater than the first hydrogen content.

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in package body comprising dielectric layers and electrically conductive layers, and where an external dielectric coating, such as a solder resist coating is provided on one or both external sides of the package body. The solder resist coating is patterned to avoid inside corners, e.g. the solder resist does not extend around or between electrical contact areas and thermal pads. It is observed that in conventional solder resist coatings, during thermal cycling, cracks tend to initiate at high stress points, such as at sharp inside corners. A solder resist layout which omits inside corners, and comprises outside corners only, is demonstrated to provide significantly improved resistance to initiation and propagation of cracks. Where inside corners are unavoidable, they are appropriately radiused to reduce stress.

Abstract: There is provided an epitaxial substrate, including: a GaN substrate whose main surface is a c-plane; and a GaN layer epitaxially grown on the main surface, wherein the main surface includes a region where an off-angle is 0.4° or more, and an E3 trap concentration in the GaN layer grown on the region is 3.0×1013 cm?3 or less.

Abstract: The application relates to a semiconductor transistor device, having a source region, a body region including a channel region extending in a vertical direction, a drain region, a gate region arranged aside the channel region in a lateral direction, and a body contact region made of an electrically conductive material, wherein the body contact region forms a body contact area, the body contact region being in an electrical contact with the body region via the body contact area, and wherein the body contact area is tilted with respect to the vertical direction and the lateral direction.

Abstract: Embodiments of the present disclosure are directed towards a memory device including a top wordline contact located in a region that is protected from erosion during a planarization process, e.g., chemical mechanical polish (CMP). In embodiments, a plurality of wordlines are formed in a stack of multiple layers and a plurality of wordline contacts are formed to intersect with the plurality of wordlines. In embodiments, the stack forms a staircase and each of the plurality of wordline contacts lands on a corresponding each of the wordlines proximate to an edge of the staircase such that a top wordline contact lands in a region on a top wordline previously covered by a sacrificial layer. In some embodiments, the region is proximate to a raised notch at an edge of the staircase. Other embodiments may be described and claimed.

Abstract: A semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed, wherein the plurality of conductive pillars disposed by the same side of the upper semiconductor device and the upper semiconductor device comprises a cantilever part cantilevered over the at least one lower semiconductor device. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over the upper semiconductor device and the encapsulating material.

Abstract: In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

Abstract: Disclosed is a semiconductor device and a method for manufacturing the same and, more particularly, a semiconductor device and a method for manufacturing the same seeking to improve on-resistance and breakdown voltage characteristics compared to existing semiconductor structures by forming an air gap under a gate field plate adjacent to a gate electrode or over a drift region of the semiconductor device.

Abstract: A method of etching an indium gallium zinc oxide (IGZO) structure is provided. In one aspect, the method includes exposing the IGZO structure to a reactant flow including a hydrocarbon-based reactant. Thereby, a reactant layer is formed on the IGZO structure. The method also includes exposing the reactant layer formed on the IGZO structure to an argon flow. Thereby, one or more reactant molecules are removed from the reactant layer. The one or more reactant molecules, which are removed from the reactant layer formed on the IGZO structure, are removed together with one or more IGZO molecules, thus leading to an etching of the IGZO structure.

Abstract: A wide-band gap semiconductor device and a method of manufacturing the same are provided. The wide-band gap semiconductor device of the disclosure includes a substrate, an epitaxial layer, an array of merged PN junction Schottky (MPS) diode, and an edge termination area surrounding the array of MPS diode. The epitaxial layer includes a first plane, a second plane, and trenches between the first plane and the second plane. The array of MPS diode is formed in the first plane of the epitaxial layer. The edge termination area includes a floating ring region having floating rings formed in the second plane of the epitaxial layer, and a transition region between the floating ring region and the array of MPS diode. The transition region includes a PIN diode formed in the plurality of trenches and on the epitaxial layer between the trenches.

Abstract: A manufacturing method of a semiconductor device includes forming a contact opening in a wafer. The wafer includes a substrate, a gate structure over the substrate and a dielectric layer over the substrate and surrounding the gate structure, and the contact opening passes through the dielectric layer and exposes the substrate. A recess is formed in the substrate such that the recess is connected to the contact opening. An oxidation process is performed to convert a portion of the substrate exposed in the recess to form a protection layer lining a sidewall and a bottom surface of the recess. The protection layer is etched back to remove a first portion of the protection layer in contact with the bottom surface of the recess of the substrate. A metal alloy structure is formed at the bottom surface of the recess of the substrate.

Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.

Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole micro-LED chip, the multiple micro-LEDs sharing the light emitting layer. The micro-LED chip further includes: a top spacer formed on a top surface of the light emitting layer; a bottom spacer formed on a bottom surface of the light emitting layer; and an isolation structure formed between adjacent micro-LEDs.

Abstract: The present application discloses a method for manufacturing fin field effect transistors, comprising: step 1: performing first time etching to form top portions of fins, each of the top portions is divided into a first section and a second section; step 2: forming sacrificial sidewalls on the side surfaces of the second section but not on the side surfaces of the first section; step 3: forming a doped dielectric layer to coat the side surfaces of the first section; step 4: performing a dopant drive process to diffuse dopants of the doped dielectric layer into the first section; step 5: removing the doped dielectric layer and the sacrificial sidewalls; step 6: performing second time etching to form bottom portions of the fins; and step 7: forming a dielectric isolation layer between adjacent fins.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked layer body including conductive layers stacked to be apart from each other in a first direction, and including a stair-like end with rising parts and terrace parts, wherein successive first conductive layers including an uppermost conductive layer function as select gate lines for a NAND string, and a first contact connected to the uppermost conductive layer provided to correspond to a first rising part which is an uppermost one of the rising parts. The first contact passes through the uppermost conductive layer to be further connected to a first conductive layer adjacent to the uppermost conductive layer.

Abstract: A display apparatus including an organic light-emitting display panel and a touch sensing unit disposed on the organic light-emitting display panel is disclosed. The touch sensing unit includes a touch electrode and a wiring part connected to the touch electrode. The wiring part of the touch sensing unit passes a protruding member disposed on a non-display region of the organic light-emitting display panel, and forms a first wiring part which does not overlap the protruding member, a second wiring part overlapping the protruding part, and a connection wiring part disposed between the first and second wiring parts and having a wiring width less than the first and second wiring parts so as to overlap an edge of the protruding member.

Abstract: A display device includes: ferritin encaging a first quantum dot and modified with a first peptide bound to a first pixel electrode; and ferritin encaging a second quantum dot and modified with a second peptide bound to a second pixel electrode. A first metal material and a second metal material are of different types.

Abstract: A photodetector, a preparation method for a photodetector, a photodetector array and a photodetection terminal. The photodetector comprises a substrate (11) and an optical resonant cavity (10) formed on the substrate (11).