Patents Examined by Shahed Ahmed
  • Patent number: 11147851
    Abstract: A method of fabricating an electronic power module by additive manufacturing, the electronic module including a substrate having an electrically insulating plate presenting opposite first and second faces, with a first metal layer arranged directly on the first face of the insulating plate, and a second metal layer arranged directly on the second face of the insulating plate. At least one of the metal layers is made by a step of depositing a thin layer of copper and a step of annealing the metal layer, and the method further includes a step of forming at least one thermomechanical transition layer on at least one of the first and second metal layers, the at least one thermomechanical transition layer including a material presenting a coefficient of thermal expansion that is less than that of the metal of the metal layer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: October 19, 2021
    Assignee: SAFRAN
    Inventors: Rabih Khazaka, St├ęphane Azzopardi, Donatien Henri Edouard Martineau
  • Patent number: 11152505
    Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alexei Sadovnikov, Andrew Derek Strachan, Henry Litzmann Edwards, Dhanoop Varghese, Xiaoju Wu, Binghua Hu, James Robert Todd
  • Patent number: 11145782
    Abstract: A method for processing an integrated optical circuit chip includes securing a panel dam around a periphery of an array of integrated optical circuit chips that share a substrate. The method also includes filling an area circumscribed by the panel dam with an insulating polymer to a level below a top surface of the integrated optical circuit chips. The method further includes singulating a given integrated optical circuit chip in the array of integrated optical circuit chips.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: October 12, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jane Qian Liu, Gary Philip Thomson
  • Patent number: 11145643
    Abstract: The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a plasma-induced damage (PID) protection device capable of, without increasing a chip area, releasing a large PID with high efficiency and protecting an element to be protected from the PID with higher accuracy. There are provided a protection metal-oxide-semiconductor field-effect transistor (MOSFET) that includes a drain connected to a gate electrode of a MOSFET to be protected and a grounded source and protects the MOSFET to be protected from a plasma-induced damage (PID), and a dummy antenna connected to a gate electrode of the protection MOSFET, the dummy antenna turning on the protection MOSFET prior to the MOSFET to be protected due to PID charge. The present disclosure can be applied to a semiconductor device.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: October 12, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yohei Hiura
  • Patent number: 11133228
    Abstract: A semiconductor integrated circuit includes: a semiconductor monocrystalline region; an insulating film provided on a main surface of the semiconductor monocrystalline region; a conductive layer having a rectangular shape provided on the insulating film and including at least a polycrystalline layer of p-type; electric-field relaxing layers having a lower specific resistivity than the conductive layer and each including a polycrystalline layer of n-type so as to be arranged on both sides of the conductive layer in a direction perpendicular to a current-flowing direction; a high-potential-side electrode in ohmic contact with the conductive layer at one end of the conductive layer in the current-flowing direction; and a low-potential-side electrode in ohmic contact with the conductive layer and the respective electric-field relaxing layers at another end of the conductive layer opposed to the one end in the current-flowing direction, and having a lower potential than the high-potential-side electrode.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: September 28, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hideaki Katakura
  • Patent number: 11133300
    Abstract: A semiconductor device has first second-conductivity-type high-concentration regions, second second-conductivity-type high-concentration regions, third second-conductivity-type high-concentration regions, and fourth second-conductivity-type high-concentration regions. The first connecting regions each connect a portion of each of the first second-conductivity-type high-concentration regions and a portion of each of the second second-conductivity-type high-concentration regions. The second connecting regions each connect a portion of each of the third second-conductivity-type high-concentration regions and a portion of each of the fourth second-conductivity-type high-concentration regions. A ratio of a mathematical area of the first connecting regions to a mathematical area of the second second-conductivity-type high-concentration regions is greater than a ratio of a mathematical area of the second connecting regions to a mathematical area of the fourth second-conductivity-type high-concentration regions.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: September 28, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki Hoshi
  • Patent number: 11127748
    Abstract: A semiconductor device includes a substrate, a first insulating layer, a second insulating layer above the first insulating layer, a void space between the first and second insulating layers, and contact electrodes extending through the first insulating layer, the void space, and the second insulating layer. Each of the contact electrodes includes a first end facing the substrate, a second end opposite to the first end, and a first width portion between the first end and the second end. The first width portion has a width in a second direction parallel to the substrate that is greater than a width of the first end in the second direction and a width of the second end in the second direction. The first width portion is within the void space.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 21, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shizuka Kutsukake, Hiroshi Matsumoto, Hiroto Saito
  • Patent number: 11128101
    Abstract: A transistor outline package is provided that includes a header having an upper surface, a lower surface, an inner surface, and a mounting area for an optoelectronic component in the inner surface. The header has a signal pin configured to connect an optoelectronic component. The signal pin is disposed in a feedthrough and protrudes from the lower surface. A printed circuit board attached on the signal pin substantially coaxially thereto. The printed circuit board is mechanically and electrically connected to the header by a metal block arranged adjacent to the feedthrough to provide grounding.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: September 21, 2021
    Assignee: SCHOTT AG
    Inventors: Robert Hettler, Artit Aowudomsuk, Kenneth Tan, Karsten Droegemueller
  • Patent number: 11121170
    Abstract: The present invention suggests a method for manufacturing a micro-array light emitting diode comprising: a step for forming a semiconductor lamination structure by stacking an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a substrate; a step for forming a plurality of p-type electrodes so as to be arranged two-dimensionally apart from each other on the p-type semiconductor layer; and a step for forming an isolation part in the p-type semiconductor layer exposed between the plurality of p-type electrodes in a self-aligning manner.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: September 14, 2021
    Inventors: Joon Seop Kwak, In Yeol Hong, Tae Kyoung Kim
  • Patent number: 11121253
    Abstract: A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: September 14, 2021
    Assignee: Key Foundry Co., Ltd.
    Inventors: Jin Seong Chung, Tae Hoon Lee
  • Patent number: 11121214
    Abstract: A semiconductor device includes a substrate, semiconductor 2-D material layer, a conductive 2-D material layer, a gate dielectric layer, and a gate electrode. The semiconductor 2-D material layer is over the substrate. The conductive 2-D material layer extends along a source/drain region of the semiconductor 2-D material layer, in which the conductive 2-D material layer comprises a group-IV element. The gate dielectric layer extends along a channel region of the semiconductor 2-D material layer. The gate electrode is over the gate dielectric layer.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 14, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yen Lin, Kuan-Chao Chen, Hsuan-An Chen, Lun-Ming Lee
  • Patent number: 11121264
    Abstract: A junction field effect transistor includes a first semiconductor layer of first conductivity type, an element isolation insulator disposed on the first semiconductor layer to partition an active area, a second semiconductor layer of second conductivity type, on the first semiconductor layer in the active area, and having an end in a first direction separated from the element isolation insulator, a source layer of second conductivity type, on the second semiconductor layer, the source layer having an impurity concentration higher than that of the second semiconductor layer, a drain layer of second conductivity type, on the second semiconductor layer, and separated from the source layer in a second direction, the drain layer having an impurity concentration higher than that of the second semiconductor layer, and a gate layer of first conductivity type, on the second semiconductor layer, and between and separated from the source and drain layers.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 14, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hidekazu Inoto, Osamu Takata, Naozumi Terada, Hiroyoshi Kitahara
  • Patent number: 11114450
    Abstract: A one-time programmable (OTP) memory device includes a plurality of unit cells which are respectively located at cross points of word lines and bit lines. Each unit cell includes a selection transistor and a storage transistor coupled in series. The selection transistor includes a drain region and a common junction region separated by a first channel region and includes a selection gate structure disposed on the first channel region. The storage transistor includes a source region and the common junction region separated by a second channel region and includes a floating gate structure disposed on the second channel region. A length of an overlapping region between the source region and the floating gate structure in a channel length direction of the storage transistor is less than a length of an overlapping region between the common junction region and the floating gate structure in the channel length direction.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: September 7, 2021
    Assignee: SK hynix system ic Inc.
    Inventor: Kwang Il Choi
  • Patent number: 11107925
    Abstract: A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11101380
    Abstract: An apparatus, an integrated circuit die, and a method of fabricating a group III-nitride (III-N) integrated RF front-end circuit are disclosed. The apparatus includes a III-N integrated radio frequency (RF) front-end circuit that includes a semiconductor substrate, a plurality of functional blocks, each of the plurality of functional blocks comprising a III-N structure on the semiconductor substrate. The III-N integrated RF front-end circuit is to be coupled to an antenna.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 11101439
    Abstract: In one aspect, composite materials including a thin-film layer of lateral p-n junctions are described herein, which can be employed in circuits or various components of electrical devices. Briefly, a composite material comprises a thin-film layer including p-type regions alternating with n-type regions along a face of the thin-film layer, the p-type regions comprising electrically conductive particles dispersed in a first organic carrier and the n-type regions comprising electrically conductive particles dispersed in a second organic carrier, wherein p-n junctions are established at interfaces between the p-type and n-type regions. As described further herein, the thin-film layer is flexible, permitting the thin-film to be folded or arranged into a number of configurations to provide various circuits or components of electrical devices.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 24, 2021
    Assignee: Wake Forest University
    Inventor: David Carroll
  • Patent number: 11094531
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a gate, and a phosphorus containing dielectric layer. The gate is on the substrate. The phosphorus containing dielectric layer is on the gate. The phosphorus containing dielectric layer has a varied phosphorus dopant density distribution profile.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: August 17, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhen-Zhen Wang, Jian-Jun Zhang
  • Patent number: 11094815
    Abstract: An object of the present invention is to provide a highly reliable semiconductor device by preventing precipitation of an oxide to prevent peeling of a resin layer. The semiconductor device includes: a resin layer provided so that at least a part of the resin layer extends on a front surface of a semiconductor layer on an outer peripheral side with respect to an outer peripheral end of a field insulating film; and a floating well region spaced apart from a termination well region in a surface layer of the semiconductor layer, the floating well region formed to be in contact with an outer peripheral end of the field insulating film to extend to the outer peripheral side with respect to the outer peripheral end of the field insulating film.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: August 17, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kohei Ebihara, Naruto Miyakawa
  • Patent number: 11094602
    Abstract: A semiconductor device package includes a carrier, a first interposer disposed and a second interposer. The second interposer is stacked on the first interposer, and the first interposer is mounted to the carrier. The combination of the first interposer and the second interposer is substantially T-shaped.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: August 17, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hao-Chih Hsieh, Tun-Ching Pi, Sung-Hung Chiang, Yu-Chang Chen
  • Patent number: 11088290
    Abstract: Provided is a semiconductor apparatus in which the buried region includes an end portion buried region continuously disposed from a region below the contact opening up to a region below the interlayer dielectric film while passing below an end portion of the contact opening in a cross section perpendicular to the upper surface of the semiconductor substrate, and the end portion buried region disposed below the interlayer dielectric film is shorter than the end portion buried region disposed below the contact opening in a first direction in parallel with the upper surface of the semiconductor substrate.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: August 10, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Yuichi Onozawa